公开(公告)号：US11081185B2

公开(公告)日：2021-08-03

申请号：US16444410

申请日：2019-06-18

Applicant: SanDisk Technologies LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C16/08 ,  G11C16/14 ,  H01L23/528 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  H01L25/18

Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.

公开(公告)号：US20210082506A1

公开(公告)日：2021-03-18

申请号：US17102430

申请日：2020-11-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C16/04 ,  H01L27/11524 ,  G11C16/08 ,  G11C16/16 ,  H01L27/11529 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/24

Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.

公开(公告)号：US20230041950A1

公开(公告)日：2023-02-09

申请号：US17397846

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam ,  Hiroyuki Ogawa

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L23/528 ,  H01L23/522 ,  G11C8/14 ,  G11C5/06

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20230038557A1

公开(公告)日：2023-02-09

申请号：US17397777

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H01L27/11582 ,  G11C16/08 ,  G11C16/24 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11573

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20210142841A1

公开(公告)日：2021-05-13

申请号：US16683209

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/56 ,  H01L27/06

Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.

公开(公告)号：US10854619B2

公开(公告)日：2020-12-01

申请号：US16213180

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  H01L27/11526

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US12284807B2

公开(公告)日：2025-04-22

申请号：US17397777

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hiroyuki Ogawa ,  Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H10B43/27 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US11889694B2

公开(公告)日：2024-01-30

申请号：US17397846

申请日：2021-08-09

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam ,  Hiroyuki Ogawa

IPC: G11C11/34 ,  H10B43/27 ,  G11C5/06 ,  H01L23/522 ,  G11C8/14 ,  H01L23/528 ,  H10B41/10 ,  H10B41/35

CPC classification number: H10B43/27 ,  G11C5/063 ,  G11C8/14 ,  H01L23/5226 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/35

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US11335671B2

公开(公告)日：2022-05-17

申请号：US16886164

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Zhixin Cui ,  Rajdeep Gautam

IPC: H01L25/18 ,  H01L23/00 ,  G11C7/12 ,  H01L25/00 ,  G11C7/06

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US11189335B2

公开(公告)日：2021-11-30

申请号：US16683209

申请日：2019-11-13

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze ,  Ken Oowada

IPC: G11C11/408 ,  G11C7/14 ,  G11C11/4094 ,  H01L27/06 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/4091

Abstract: A three-dimensional (3D) memory is provided, including a memory array chip and a complementary metal-oxide semiconductor (CMOS) chip disposed on the memory array chip. The memory chip provides double write/read throughput and includes a lower region with a lower array of memory cells, lower word lines, and a lower bit line, while an upper region includes an upper array of memory cells, upper word lines, and an upper bit line. A source line is disposed between the lower and upper regions and is connected to both the lower array of memory cells and the upper array of memory cells.