公开(公告)号：US20210358553A1

公开(公告)日：2021-11-18

申请号：US17360572

申请日：2021-06-28

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Technology is disclosed herein for concurrently programming the same data pattern in multiple sets of non-volatile memory cells. Voltage are applied to bit lines in accordance with a data pattern. A select voltage is applied to drain select gates of multiple sets of NAND strings. The system concurrently applies a program pulse to control gates of a different set of selected memory cells in each respective set of the multiple sets of the NAND strings while the select voltage is applied to the drain select gates of the multiple sets of the NAND strings and the voltages are applied to the plurality of bit lines to concurrently program the data pattern into each set of the selected memory cells.

公开(公告)号：US10978156B2

公开(公告)日：2021-04-13

申请号：US16024002

申请日：2018-06-29

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C8/12 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US20180357123A1

公开(公告)日：2018-12-13

申请号：US15934565

申请日：2018-03-23

Applicant: SanDisk Technologies LLC

Inventor： Yibo Yin ,  Henry Zhang ,  Po-Shen Lai ,  Vijay Chinchole ,  Spyridon Georgakis ,  Yan Li ,  Hiroyuki Mizukoshi ,  Toru Miwa ,  Jayesh Pakhale ,  Tz-Yi Liu

IPC: G06F11/10

CPC classification number: G06F11/1016 ,  G06F11/1064

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.

公开(公告)号：US20240136001A1

公开(公告)日：2024-04-25

申请号：US18357489

申请日：2023-07-23

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Jiahui Yuan ,  Toru Miwa

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L25/0657

Abstract: A memory system programs memory cells connected to a selected word line by applying doses of programming and performing program-verify between doses. An efficient and low current program-verify operation includes: while scanning the results of a previous program-verify operation, ramp up voltages on the select lines for the next program-verify operation without waiting for the scan to complete and ramp up voltages on unselected word lines for the next program-verify operation following a step signal (so that voltage applied to the unselected word lines rise in steps) without waiting for the scan to complete.

公开(公告)号：US11342028B2

公开(公告)日：2022-05-24

申请号：US17227820

申请日：2021-04-12

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Aaron Lee ,  Gerrit Jan Hemink ,  Ken Oowada ,  Toru Miwa

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C8/18 ,  G11C8/12

Abstract: Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.

公开(公告)号：US20210134828A1

公开(公告)日：2021-05-06

申请号：US16675800

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Naoki Ookuma ,  Hiroki Yabe ,  Koichiro Hayashi ,  Takuya Ariki ,  Toru Miwa

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11556 ,  H01L21/02 ,  H01L21/28 ,  H01L27/11573

Abstract: A non-volatile memory apparatus is provided and includes a substrate having a major surface extending longitudinally. A stack of first and second sets of word lines and insulating layers extends along and over the major surface longitudinally and alternating with and overlying one another vertically to define a device region. The first and second sets of word lines each respectively extends longitudinally beyond a first and second side of the device region a decreasing longitudinal distance from the device region as a vertical distance from the major surface increases to define first and second stepped contact regions. Word line contacts extend vertically in the first and second stepped contact regions. The second set of word lines in the first stepped contact region do not contact the word line contacts and the first set of word lines in the second stepped contact region do not contact the word line contacts.

公开(公告)号：US10854619B2

公开(公告)日：2020-12-01

申请号：US16213180

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11548 ,  H01L27/11573 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30 ,  H01L27/11526

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US12270853B2

公开(公告)日：2025-04-08

申请号：US18221824

申请日：2023-07-13

Applicant: SanDisk Technologies LLC

Inventor： Toru Miwa ,  Takashi Murai ,  Hiroyuki Ogawa ,  Nisha Padattil Kuliyampattil

IPC: G01R31/28 ,  G01R1/073 ,  H01L21/66 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor wafer includes pairs of semiconductor dies having test pads which are electrically coupled to each other to enable testing of pairs of semiconductor dies together at the same time. In this way, even wafers having large numbers of semiconductor dies can be tested with a semiconductor test assembly in a single touch-down test process.

公开(公告)号：US11625172B2

公开(公告)日：2023-04-11

申请号：US17349306

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G06F3/06

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. One or more initial pages of data are programmed into both a primary block and a first backup block in a first program pass. A power loss then occurs which can corrupt the data or otherwise prevent reading of the one or more initial pages of data from the primary block. The one or more initial pages of data are read from the first backup block and used to perform a second program pass in which one or more additional pages of data are programmed into the primary block. Single bit per cell data can be stored in a second backup block to decode the one or more initial pages of data as read from the first backup block.

公开(公告)号：US11551781B1

公开(公告)日：2023-01-10

申请号：US17349321

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Toru Miwa ,  Ken Oowada ,  Gerrit Jan Hemink

IPC: G11C16/26 ,  G11C29/00 ,  G11C29/02 ,  G11C16/34 ,  G11C16/10

Abstract: Apparatuses and techniques are described for programming data in memory cells while concurrently storing backup data. Initial pages of multiple bit per cell data are encoded to obtain at least first and second pages of single bit per cell data. The initial pages of multiple bit per cell data are programmed into a primary set of memory cells, while concurrently the first and second pages of single bit per cell data are programmed into first and second backup sets of memory cells, respectively. In the event of a power loss, the first and second pages of single bit per cell data are read from the first and second backup sets of memory cells, and decoded to recover the initial pages of multiple bit per cell data.