公开(公告)号：US10811109B2

公开(公告)日：2020-10-20

申请号：US16233723

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US20200312414A1

公开(公告)日：2020-10-01

申请号：US16900015

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/24 ,  G11C16/10 ,  G11C11/56

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US10665301B1

公开(公告)日：2020-05-26

申请号：US16245491

申请日：2019-01-11

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  G11C11/56 ,  G11C16/26

Abstract: Techniques are provided for optimizing a program operation in a memory device to compensate for program speed variations due to block oxide thinning. In one approach, during a program operation, a program voltage which indicates program speed is acquired from sub-blocks with the highest and lowest program speeds. An initial program voltage for intermediate sub-blocks can be determined based on the acquired program voltages and the positions of the intermediate sub-blocks. The technique can accommodate a loss of one or both acquired program voltages if the programming is interrupted. In another approach, a program voltage which indicates program speed is acquired from one sub-block, and for a later-programmed sub-block, an appropriate offset is located from a table and summed with the acquired program voltage to determine an optimum initial program voltage.

公开(公告)号：US10510413B1

公开(公告)日：2019-12-17

申请号：US16057423

申请日：2018-08-07

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Ching-Huang Lu

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/34 ,  G11C16/08 ,  G11C16/28 ,  G11C16/16

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In a first program pass of a multi-pass program operation, pass voltages of the word lines adjacent to a selected word line are adjusted to increase electron injection in a portion of a charge-trapping layer between the selected word line and an adjacent source side unselected word line. In a second, final program pass of the multi-pass program operation, the pass voltages are adjusted to reduce electron injection in the portion of the charge-trapping layer between the selected word line and the adjacent source side unselected word line.

公开(公告)号：US10008271B1

公开(公告)日：2018-06-26

申请号：US15693982

申请日：2017-09-01

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Ching-Huang Lu ,  Yingda Dong

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/30 ,  G11C16/08 ,  G11C7/14

CPC classification number: G11C16/10 ,  G11C7/14 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3445 ,  G11C16/3459 ,  G11C2213/75

Abstract: A memory device and associated techniques for reducing charge loss in a select gate transistor. A dummy memory cell is weakly programmed using a hot electron injection type of disturb to reduce the movement of holes toward the adjacent select gate transistor in a common charge trapping layer. The weak programming can occur in a program loop, e.g., in a transition between a pre-charge phase and a program phase, or in an erase loop, just after the erase of dummy and data memory cells. The weak programming does not involve a time penalty since it is concurrent with other operations. The disturb can be provided by increasing the control gate voltage of the dummy memory cell and/or decreasing the control gate voltage of the select gate transistor.

公开(公告)号：US10923197B2

公开(公告)日：2021-02-16

申请号：US16922037

申请日：2020-07-07

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C11/34 ,  G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US10854300B2

公开(公告)日：2020-12-01

申请号：US16898145

申请日：2020-06-10

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Vinh Diep ,  Zhengyi Zhang

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24

Abstract: Techniques are described for programming memory cells with reduced widening of the threshold voltage distributions. Bit line voltages are adjusted during verify tests for memory cells assigned to the upper data state in a pair of adjacent data states which are concurrently verified. An elevated bit line voltage is applied and then stepped up in successive program loops. A lower, fixed bit line voltage is used for verifying the lower data state in the pair of adjacent data states. In one option, the step size increases progressively over the program loops. In another option, the minimum level of the elevated bit line voltage is lower for higher data states. In another option, the minimum level of the elevated bit line voltage is set as a function of data states, program-erase cycles and/or temperature.

公开(公告)号：US10741253B1

公开(公告)日：2020-08-11

申请号：US16280297

申请日：2019-02-20

Applicant: SanDisk Technologies LLC

Inventor： Ching-Huang Lu ,  Ashish Baraskar ,  Vinh Diep

IPC: G11C7/00 ,  G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  G11C16/34 ,  H01L27/11578

Abstract: Techniques are provided for optimizing an erase operation in a memory device to compensate for erase speed variations due to blocking oxide thinning In an erase operation for a block, the channels of NAND strings in different sub-blocks can be charged up by different amounts. One approach adjusts the control gate voltage of a first select gate transistor in a NAND string. This adjusts the amount of holes generated in the channel due to gate-induced drain leakage. Another approach adjusts the control gate voltage of additional select gate transistors in the NAND string to adjust the conductivity of the adjacent channel regions. Another approach applies different bit line voltages to different rows of NAND strings in each sub-block.

公开(公告)号：US20200211663A1

公开(公告)日：2020-07-02

申请号：US16233723

申请日：2018-12-27

Applicant: SanDisk Technologies LLC

Inventor： Ashish Baraskar ,  Ching-Huang Lu ,  Vinh Diep ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/26

Abstract: Techniques are provided to reduce neighbor word line interference and charge loss in a multi-pass program operation. In one implementation, the first pass of a multi-pass program operation uses one or more program pulses without performing associated verify tests. The memory cells may be programmed to different intermediate threshold voltage (Vth) distributions in the first program pass. Different bit line voltages can be used to obtain the different intermediate Vth distributions when the single program pulse is applied. In other cases, multiple program pulses are applied without performing verify tests. The intermediate Vth distributions can be provided for the memory cells assigned to the higher data states but not the lower data states, or for memory cells assigned to both the higher and lower data states.

公开(公告)号：US20190311772A1

公开(公告)日：2019-10-10

申请号：US15948761

申请日：2018-04-09

Applicant: SanDisk Technologies LLC

Inventor： Vinh Diep ,  Ching-Huang Lu ,  Zhengyi Zhang ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/14

Abstract: Apparatuses and techniques are described for programming memory cells with a narrow threshold voltage (Vth) distribution in a memory device. In one approach, the final pass of a multi-pass program operation on a word line WLn includes applying a variable voltage to WLn+1 during verify tests on WLn. The variable voltage (Vread) can be an increasing function of the verify voltage on WLn, and thus a function of the data state for which the verify test is performed. In one approach, Vread on WLn+1 is stepped up with each increase in the verify voltage on WLn. The step size in Vread can be the same as, or different than, the step size in the verify voltage. Vread can be different for each different verify voltage, or multiple verify voltages can be grouped for use with a common Vread.