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    ON-THE-FLY MULTIPLEXING SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES
    11.
    发明申请
    ON-THE-FLY MULTIPLEXING SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES 有权

    公开(公告)号：US20230095127A1

    公开(公告)日：2023-03-30

    申请号：US17731971

    申请日：2022-04-28

    Applicant: SanDisk Technologies LLC

    Inventor： YenLung Li ,  Siddarth Naga Murty Bassa ,  Chen Chen ,  Hua-Ling Cynthia Hsu

    IPC: G06F3/06

    Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

    VERTICAL COMPRESSION SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES WITH DATA LATCH GROUPS
    12.
    发明申请
    VERTICAL COMPRESSION SCHEME FOR COMPRESSED SOFT BIT DATA IN NON-VOLATILE MEMORIES WITH DATA LATCH GROUPS 有权

    公开(公告)号：US20230085405A1

    公开(公告)日：2023-03-16

    申请号：US17731961

    申请日：2022-04-28

    Applicant: SanDisk Technologies LLC

    Inventor： Hua-Ling Cynthia Hsu ,  YenLung Li

    IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

    Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

    USE OF DATA LATCHES FOR PLANE LEVEL COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES
    14.
    发明申请
    USE OF DATA LATCHES FOR PLANE LEVEL COMPRESSION OF SOFT BIT DATA IN NON-VOLATILE MEMORIES 有权

    公开(公告)号：US20230085776A1

    公开(公告)日：2023-03-23

    申请号：US17742982

    申请日：2022-05-12

    Applicant: SanDisk Technologies LLC

    Inventor： Siddarth Naga Murty Bassa ,  YenLung Li ,  Hua-Ling Cynthia Hsu

    IPC: G11C7/10 ,  G11C7/06 ,  G11C7/12

    Abstract: For a non-volatile memory that uses hard bit and soft bit data in error correction operations, to reduce the amount of soft bit data that needs to be transferred from a memory to the controller and improve memory system performance, the soft bit data can be compressed before transfer. After the soft bit data is read and stored into the internal data latches associated with the sense amplifiers, it is compressed within these internal data latches. The compressed soft bit data can then be transferred to the transfer data latches of a cache buffer, where the compressed soft bit data can be consolidated and transferred out over an input-output interface. Within the input-output interface, the compressed data can be reshuffled to put into logical user data order if needed.

    Centralized fixed rate serializer and deserializer for bad column management in non-volatile memory
    15.
    发明授权
    Centralized fixed rate serializer and deserializer for bad column management in non-volatile memory 有权

    公开(公告)号：US11386961B2

    公开(公告)日：2022-07-12

    申请号：US16722538

    申请日：2019-12-20

    Applicant: SanDisk Technologies LLC

    Inventor： YenLung Li ,  Chen Chen ,  Min Peng ,  Mitsuyuki Watanabe

    IPC: G06F3/00 ,  G11C16/10 ,  G06F13/16 ,  G11C16/26 ,  G11C16/04 ,  H03M9/00

    Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.

    CENTRALIZED FIXED RATE SERIALIZER AND DESERIALIZER FOR BAD COLUMN MANAGEMENT IN NON-VOLATILE MEMORY
    16.
    发明申请
    CENTRALIZED FIXED RATE SERIALIZER AND DESERIALIZER FOR BAD COLUMN MANAGEMENT IN NON-VOLATILE MEMORY 有权

    公开(公告)号：US20210193226A1

    公开(公告)日：2021-06-24

    申请号：US16722538

    申请日：2019-12-20

    Applicant: SanDisk Technologies LLC

    Inventor： YenLung Li ,  Chen Chen ,  Min Peng ,  Mitsuyuki Watanabe

    IPC: G11C16/10 ,  G06F13/16 ,  H03M9/00 ,  G11C16/04 ,  G11C16/26

    Abstract: In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.

    Centralized variable rate serializer and deserializer for bad column management
    17.
    发明授权
    Centralized variable rate serializer and deserializer for bad column management 有权
    集中可变速率序列化器和解串器，用于色谱柱管理不良

    公开(公告)号：US09583220B2

    公开(公告)日：2017-02-28

    申请号：US15194867

    申请日：2016-06-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Wanfang Tsai ,  YenLung Li ,  Chen Chen

    IPC: G11C7/00 ,  G11C29/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C29/82 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/808 ,  G11C2207/107

    Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

    Abstract translation: 存储器电路包括细分成多个分区的阵列，每个分区可连接到对应的一组接入电路。 串行器/解串器电路连接到数据总线和访问电路，用于在总线上的（逐字）串行格式和用于访问电路的（多字）并行格式之间转换数据。 列冗余电路连接到串行器/解串器电路，以提供关于阵列的有缺陷的列信息。 在将数据从串行格式转换为并行格式时，串行器/解串器电路基于指示位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。 在将数据从并行转换为串行格式时，串行器/解串器电路基于指示该位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。

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