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    Hierarchical fail bit counting circuit in memory device
    1.
    发明授权
    Hierarchical fail bit counting circuit in memory device 有权

    公开(公告)号：US10297337B2

    公开(公告)日：2019-05-21

    申请号：US15669739

    申请日：2017-08-04

    Applicant: SanDisk Technologies LLC

    Inventor： Wanfang Tsai ,  Hung-Szu Lin ,  Yi-Fang Chen

    IPC: G11C29/44 ,  H03K23/40

    Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

    Centralized variable rate serializer and deserializer for bad column management
    2.
    发明授权
    Centralized variable rate serializer and deserializer for bad column management 有权
    集中可变速率序列化器和解串器，用于色谱柱管理不良

    公开(公告)号：US09490035B2

    公开(公告)日：2016-11-08

    申请号：US14104817

    申请日：2013-12-12

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Wanfang Tsai ,  YenLung Li ,  Chen Chen

    IPC: G11C7/00 ,  G11C29/00

    CPC classification number: G11C29/82 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/808 ,  G11C2207/107

    Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

    Abstract translation: 存储器电路包括细分成多个分区的阵列，每个分区可连接到对应的一组接入电路。 串行器/解串器电路连接到数据总线和访问电路，用于在总线上的（逐字）串行格式和用于访问电路的（多字）并行格式之间转换数据。 列冗余电路连接到串行器/解串器电路，以提供关于阵列的有缺陷的列信息。 在将数据从串行格式转换为并行格式时，串行器/解串器电路基于指示位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。 在将数据从并行转换为串行格式时，串行器/解串器电路基于指示该位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。

    Hierarchical Fail Bit Counting Circuit In Memory Device
    3.
    发明申请
    Hierarchical Fail Bit Counting Circuit In Memory Device 审中-公开

    公开(公告)号：US20190043603A1

    公开(公告)日：2019-02-07

    申请号：US15669739

    申请日：2017-08-04

    Applicant: SanDisk Technologies LLC

    Inventor： Wanfang Tsai ,  Hung-Szu Lin ,  Yi-Fang Chen

    IPC: G11C29/44 ,  H03K23/40

    Abstract: Apparatuses and techniques for counting 0 or 1 bits in a set of bits using both serial and parallel processes. The counting process includes a hierarchy in which the count from different parallel processes at one level in the hierarchy are passed to a smaller number of different parallel processes at a lower level in the hierarchy. A final count is obtained by an accumulator below the lowest level of the hierarchy. The position and configuration of the circuits can be set to equalize a number of circuits which process the different bits, so that a maximum delay relative to the accumulator is equalized.

    Bad column management with data shuffle in pipeline
    4.
    发明授权
    Bad column management with data shuffle in pipeline 有权

    公开(公告)号：US10120816B2

    公开(公告)日：2018-11-06

    申请号：US15458561

    申请日：2017-03-14

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Wanfang Tsai ,  Yan Li

    IPC: G06F13/16 ,  G06F5/06 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C29/00 ,  G11C7/10

    Abstract: Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

    Centralized variable rate serializer and deserializer for bad column management
    5.
    发明授权
    Centralized variable rate serializer and deserializer for bad column management 有权
    集中可变速率序列化器和解串器，用于色谱柱管理不良

    公开(公告)号：US09583220B2

    公开(公告)日：2017-02-28

    申请号：US15194867

    申请日：2016-06-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Wanfang Tsai ,  YenLung Li ,  Chen Chen

    IPC: G11C7/00 ,  G11C29/00 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

    CPC classification number: G11C29/82 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3404 ,  G11C29/808 ,  G11C2207/107

    Abstract: A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.

    Abstract translation: 存储器电路包括细分成多个分区的阵列，每个分区可连接到对应的一组接入电路。 串行器/解串器电路连接到数据总线和访问电路，用于在总线上的（逐字）串行格式和用于访问电路的（多字）并行格式之间转换数据。 列冗余电路连接到串行器/解串器电路，以提供关于阵列的有缺陷的列信息。 在将数据从串行格式转换为并行格式时，串行器/解串器电路基于指示位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。 在将数据从并行转换为串行格式时，串行器/解串器电路基于指示该位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。

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