公开(公告)号：US12284834B2

公开(公告)日：2025-04-22

申请号：US18777737

申请日：2024-07-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Derrick Johnson ,  Yupeng Chen ,  Ralph N. Wall ,  Mark Griswold

IPC: H10D89/60 ,  H10D84/85

Abstract: In an example, a semiconductor device includes a semiconductor substrate of a first conductivity type and a semiconductor region of the first conductivity type over the semiconductor substrate. A well region of a second conductivity type is in the semiconductor region. A doped region of the first conductivity type is in the well region. A doped region of the second conductivity type is in the well region. A doped region of the second conductivity type is in the semiconductor substrate at a bottom side. A doped region of the first conductivity type is in the semiconductor substrate at the bottom side. A first conductor is at a top side of the semiconductor region and a second conductor is at the bottom side. In some examples, one or more of doped regions at the bottom side is a patterned doped region.

公开(公告)号：US20220254920A1

公开(公告)日：2022-08-11

申请号：US17248750

申请日：2021-02-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Weize Chen ,  Sameer S. Haddad ,  Bruce B. Greenwood ,  Mark Griswold ,  Kenneth A. Bates

IPC: H01L29/788 ,  H01L29/49 ,  H01L29/66 ,  H01L29/423

Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

公开(公告)号：US12211784B2

公开(公告)日：2025-01-28

申请号：US18591340

申请日：2024-02-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mark Griswold ,  Michael J. Seddon

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/78 ,  H01L21/786 ,  H01L23/12 ,  H01L23/34 ,  H01L23/522

Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

公开(公告)号：US11545583B2

公开(公告)日：2023-01-03

申请号：US17248750

申请日：2021-02-05

Applicant: Semiconductor Components Industries, LLC

Inventor： Weize Chen ,  Sameer S. Haddad ,  Bruce B. Greenwood ,  Mark Griswold ,  Kenneth A. Bates

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

公开(公告)号：US11222840B2

公开(公告)日：2022-01-11

申请号：US16929397

申请日：2020-07-15

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mark Griswold ,  Michael J. Seddon

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/34 ,  H01L21/786 ,  H01L23/12

Abstract: Implementations of a silicon-on-insulator (SOI) die may include a silicon layer including a first side and a second side, and an insulative layer coupled directly to the second side of the silicon layer. The insulative layer may not be coupled to any other silicon layer.

公开(公告)号：US09647080B2

公开(公告)日：2017-05-09

申请号：US15040650

申请日：2016-02-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Mark Griswold ,  Ali Salih

IPC: H01L29/00 ,  H01L29/47 ,  H01L29/66 ,  H01L29/872 ,  H01L21/223 ,  H01L21/265 ,  H01L21/285 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/47 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/28537 ,  H01L29/0615 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/872 ,  H01L29/8725

Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.

公开(公告)号：US20160172458A1

公开(公告)日：2016-06-16

申请号：US15040650

申请日：2016-02-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Mark Griswold ,  Ali Salih

IPC: H01L29/47 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L29/06 ,  H01L21/223 ,  H01L29/872 ,  H01L21/285

CPC classification number: H01L29/47 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/28537 ,  H01L29/0615 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/872 ,  H01L29/8725

Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.

公开(公告)号：US20150236172A1

公开(公告)日：2015-08-20

申请号：US14181207

申请日：2014-02-14

Applicant: Semiconductor Components Industries, LLC

Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Mark Griswold ,  Ali Salih

IPC: H01L29/872 ,  H01L29/66

CPC classification number: H01L29/47 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/28537 ,  H01L29/0615 ,  H01L29/66143 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/872 ,  H01L29/8725

Abstract: A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.

Abstract translation: 肖特基器件包括在半导体材料的一部分中的势垒高度调节层。 根据一个实施例，肖特基器件由第一导电类型的半导体材料形成，该半导体材料具有从半导体材料的第一主表面延伸到半导体材料中的第二导电类型的势垒高度调节层， 小于零偏置耗尽边界。 形成与掺杂层接触的肖特基接触。

公开(公告)号：US11552193B2

公开(公告)日：2023-01-10

申请号：US17139748

申请日：2020-12-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Weize Chen ,  Mark Griswold ,  Jaroslav Pjencak

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: An embodiment of a semiconductor device may include a transistor having a first doped region and a second doped region that extend laterally underlying the source, body, and drain of the transistor. The transistor may have an embodiment that includes an additional bias contact to apply a bias potential to the first doped region and or alternately the second doped region.

公开(公告)号：US11506687B2

公开(公告)日：2022-11-22

申请号：US17011027

申请日：2020-09-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Kevin Alexander Stewart ,  Martin Kejhar ,  Radim Mlcousek ,  Arash Elhami Khorasani ,  David T. Price ,  Mark Griswold

IPC: G01R15/14 ,  G01R19/00 ,  H01L27/06 ,  H01L49/02 ,  H01L29/808

Abstract: In one embodiment, a method of forming a semiconductor device may include forming a sense resistor to receive a high voltage signal and form a sense signal that is representative of the high voltage signal. An embodiment of the sense resistor may optionally be formed overlying a polysilicon resistor. The method may also have an embodiment that may include forming a plurality of capacitors in parallel to portions of the sense resistor wherein the plurality of capacitors are connected together in series.