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公开(公告)号：US10128174B2
公开(公告)日：2018-11-13
申请号：US15204261
申请日：2016-07-07
IPC分类号： H01L23/495 , H01L29/20 , H01L29/772 , H01L21/48 , H01L23/00 , H01L25/07 , H01L29/861 , H01L23/373
摘要： In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.
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公开(公告)号：US09818677B2
公开(公告)日：2017-11-14
申请号：US15202765
申请日：2016-07-06
发明人： Chun-Li Liu , Ali Salih , Balaji Padmanabhan , Mingjiao Liu
IPC分类号： H01L23/495 , H01L23/00 , H01L25/07 , H01L23/373 , H01L33/62 , H01L29/20
CPC分类号： H01L23/49575 , H01L23/3735 , H01L23/49524 , H01L23/49531 , H01L23/49555 , H01L23/49562 , H01L23/49568 , H01L24/73 , H01L25/072 , H01L29/2003 , H01L33/62 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48245 , H01L2224/49111 , H01L2224/73221 , H01L2224/73265 , H01L2924/00014 , H01L2224/37099
摘要： In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.
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公开(公告)号：US09748224B2
公开(公告)日：2017-08-29
申请号：US14853720
申请日：2015-09-14
发明人： Balaji Padmanabhan , Prasad Venkatraman , Zia Hossain , Chun-Li Liu , Jason McDonald , Ali Salih , Alexander Young
IPC分类号： H01L29/66 , H01L27/06 , H01L27/02 , H01L23/367 , H01L29/417 , H01L29/778 , H01L29/10 , H01L21/8258 , H01L21/74 , H01L29/872 , H01L23/48 , H01L29/861 , H01L29/20
CPC分类号： H01L27/0629 , H01L21/743 , H01L21/8258 , H01L23/3677 , H01L23/481 , H01L27/0255 , H01L27/0266 , H01L27/0688 , H01L29/1087 , H01L29/2003 , H01L29/41766 , H01L29/7783 , H01L29/861 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.
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公开(公告)号：US09735095B2
公开(公告)日：2017-08-15
申请号：US15204604
申请日：2016-07-07
发明人： Balaji Padmanabhan , Prasad Venkatraman , Ali Salih , Chun-Li Liu
IPC分类号： H01L23/49 , H01L23/495 , H01L25/07 , H01L25/00
CPC分类号： H01L23/49575 , H01L23/49524 , H01L23/49531 , H01L23/49562 , H01L25/074 , H01L25/50 , H01L2224/0603 , H01L2224/16245 , H01L2224/40 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014 , H01L2224/37099
摘要： In accordance with an embodiment, a semiconductor component includes a support having first and second device receiving structures. A semiconductor device configured from a III-N semiconductor material is coupled to the support, wherein the semiconductor device has opposing surfaces. A first bond pad extends from a first portion of the first surface, a second bond pad extends from a second portion of the first surface, and a third bond pad extends from a third portion of the first surface. The first bond pad is coupled to the first device receiving portion, the drain bond pad is coupled to the second device receiving portion, and the third bond pad is coupled to the third lead. In accordance with another embodiment, a method includes coupling a semiconductor chip comprising a III-N semiconductor substrate material to a support.
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公开(公告)号：US20170025336A1
公开(公告)日：2017-01-26
申请号：US15202826
申请日：2016-07-06
发明人： Balaji Padmanabhan , Prasad Venkatraman , Ali Salih , Mihir Mudholkar , Chun-Li Liu , Jason McDonald
IPC分类号： H01L23/495 , H01L23/00
CPC分类号： H01L23/49575 , H01L23/49503 , H01L23/4951 , H01L23/49524 , H01L23/49531 , H01L23/49534 , H01L23/49541 , H01L23/49548 , H01L23/49558 , H01L23/49562 , H01L24/40 , H01L24/41 , H01L24/45 , H01L2224/40105 , H01L2224/40139 , H01L2224/40245 , H01L2224/41109 , H01L2224/41112 , H01L2224/41174 , H01L2224/48245 , H01L2224/83801 , H01L2224/84801 , H01L2924/00014 , H01L2924/10253 , H01L2924/1033 , H01L2924/13064 , H01L2924/13091 , H01L2224/37099 , H01L2224/45099
摘要： In accordance with an embodiment, a semiconductor component includes a support having a first device receiving structure and a second device receiving structure and a contact extension that is common to the first and second device receiving structures. The first device receiving structure includes a device receiving area and the second device receiving structure includes a drain contact area. A III-N based semiconductor chip has a drain bond pad bonded to the drain contact area and a source bond pad bonded to the contact extension and a gate bond pad bonded to an interconnect. A portion of the silicon based semiconductor chip is bonded to the support device receiving area. In accordance with another embodiment, a method for manufacturing the semiconductor component includes coupling a III-N based semiconductor chip to a portion of the support a silicon based semiconductor chip to another portion of the support.
摘要翻译： 根据实施例，半导体部件包括具有第一器件接收结构和第二器件接收结构的支撑件以及第一和第二器件接收结构共同的接触延伸部。 第一器件接收结构包括器件接收区域，第二器件接收结构包括漏极接触区域。 基于III-N的半导体芯片具有焊接到漏极接触区域的漏极接合焊盘和接合到接触延伸部的源极接合焊盘和键合到互连的栅极焊盘焊盘。 硅基半导体芯片的一部分结合到支撑装置接收区域。 根据另一个实施例，制造半导体部件的方法包括将基于III-N的半导体芯片与载体的一部分将硅基半导体芯片耦合到支撑体的另一部分。
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公开(公告)号：US09263598B2
公开(公告)日：2016-02-16
申请号：US14181207
申请日：2014-02-14
IPC分类号： H01L29/00 , H01L29/872 , H01L29/66 , H01L29/47
CPC分类号： H01L29/47 , H01L21/2236 , H01L21/26513 , H01L21/28537 , H01L29/0615 , H01L29/66143 , H01L29/66643 , H01L29/7839 , H01L29/872 , H01L29/8725
摘要： A Schottky device includes a barrier height adjustment layer in a portion of a semiconductor material. In accordance with an embodiment, the Schottky device is formed from a semiconductor material of a first conductivity type which has a barrier height adjustment layer of a second conductivity type that extends from a first major surface of the semiconductor material into the semiconductor material a distance that is less than a zero bias depletion boundary. A Schottky contact is formed in contact with the doped layer.
摘要翻译： 肖特基器件包括在半导体材料的一部分中的势垒高度调节层。 根据一个实施例，肖特基器件由第一导电类型的半导体材料形成，该半导体材料具有从半导体材料的第一主表面延伸到半导体材料中的第二导电类型的势垒高度调节层， 小于零偏置耗尽边界。 形成与掺杂层接触的肖特基接触。
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公开(公告)号：US20140264369A1
公开(公告)日：2014-09-18
申请号：US14203299
申请日：2014-03-10
IPC分类号： H01L29/20 , H01L29/205 , H01L29/778 , H01L29/66
CPC分类号： H01L29/7783 , H01L21/845 , H01L27/0688 , H01L27/0886 , H01L27/1211 , H01L29/045 , H01L29/0615 , H01L29/0657 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/404 , H01L29/407 , H01L29/4175 , H01L29/41791 , H01L29/42316 , H01L29/4236 , H01L29/42376 , H01L29/66431 , H01L29/66462 , H01L29/66795 , H01L29/778 , H01L29/7786 , H01L29/7787 , H01L29/7789 , H01L29/785 , H01L29/872
摘要： In one embodiment, Group III-nitride materials are used to form a semiconductor device. A fin structure is formed in the Group III-nitride material, and a gate structure, source electrodes and drain electrodes are formed in spaced relationship to the fin structure. The fin structure provides both polar and semi-polar 2DEG regions. In one embodiment, the gate structure is configured to control current flow in the polar 2DEG region. Shield conductor layers are included above the gate structure and in spaced relationship with drain regions of the semiconductor device.
摘要翻译： 在一个实施例中，III族氮化物材料用于形成半导体器件。 在III族氮化物材料中形成翅片结构，并且栅极结构，源电极和漏电极形成为与翅片结构间隔开的关系。 鳍结构提供极性和半极性2DEG区域。 在一个实施例中，门结构被配置为控制极地2DEG区域中的电流。 屏蔽导体层包括在栅极结构之上并与半导体器件的漏极区间隔开。
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公开(公告)号：US10978581B2
公开(公告)日：2021-04-13
申请号：US16387874
申请日：2019-04-18
发明人： Woochul Jeon , Chun-Li Liu , Ali Salih
IPC分类号： H01L29/778 , H01L29/423 , H01L29/06 , H01L23/58 , H01L23/495 , H01L27/088 , H01L29/16 , H01L29/20 , H01L29/40 , H01L29/417 , H01L29/10
摘要： Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.
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公开(公告)号：US10784140B2
公开(公告)日：2020-09-22
申请号：US16664758
申请日：2019-10-25
发明人： Ali Salih , Gordon M. Grivna
IPC分类号： H01L29/778 , H01L21/683 , H01L27/06 , H01L29/78 , H01L27/085 , H01L21/8258 , H01L21/304 , H01L21/306 , H01L21/56 , H01L23/31 , H01L23/00 , H01L29/40 , H01L29/417 , H01L29/16 , H01L29/20
摘要： An electronic device can include a semiconductor material and a semiconductor layer overlying the semiconductor material, wherein the semiconductor layer has a greater bandgap energy as compared to the semiconductor material. The electronic device can include a component having a high electrical field region and a low electrical field region. Within the high electrical field region, the semiconductor material is not present. In another embodiment, the component may not be present. In another aspect, a process can include providing a substrate and a semiconductor layer overlying the substrate; removing a first portion of the substrate to define a first trench; forming a first insulating layer within the first trench; removing a second portion of the substrate adjacent to first insulating layer to define second trench; and forming a second insulating layer within the second trench.
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公开(公告)号：US10770381B2
公开(公告)日：2020-09-08
申请号：US16036560
申请日：2018-07-16
IPC分类号： H01L23/495 , H01L21/48 , H01L23/00 , H01L29/20 , H01L29/772 , H01L25/07 , H01L23/373
摘要： In accordance with an embodiment, a semiconductor component includes a support and a plurality of leads. An insulated metal substrate having a first portion and a second portion bonded to the support. A semiconductor chip comprising a III-N semiconductor material is bonded to the first portion of the insulated metal substrate and a first electrical interconnect is coupled between a drain bond pad the first portion of the insulated metal substrate. A second semiconductor chip is bonded to the first electrical interconnect. A second electrical interconnect coupled between a lead of the plurality of leads and the second semiconductor chip. In accordance with another embodiment, a method of manufacturing a semiconductor component includes coupling a first semiconductor chip to a first electrically conductive layer and coupling a second semiconductor chip to a second electrically conductive layer.
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