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    Termination structure for insulated gate semiconductor device and method
    4.
    发明授权
    Termination structure for insulated gate semiconductor device and method 有权

    公开(公告)号：US10923604B2

    公开(公告)日：2021-02-16

    申请号：US16722093

    申请日：2019-12-20

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Zia Hossain

    IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/872

    Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

    Trench semiconductor device having shaped gate dielectric and gate electrode structures and method
    5.
    发明授权
    Trench semiconductor device having shaped gate dielectric and gate electrode structures and method 有权

    公开(公告)号：US10388801B1

    公开(公告)日：2019-08-20

    申请号：US15883500

    申请日：2018-01-30

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Mihir Mudholkar ,  Mohammed T. Quddus ,  Ikhoon Shin ,  Scott M. Donaldson

    IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

    Abstract: A semiconductor device includes a region of semiconductor material having first and second opposing major surfaces. A trench structure includes a trench extending into the region of semiconductor material from the first major surface, wherein the first major surface defines a first horizontal plane in a cross-sectional view. The trench structure further includes a conductive material disposed within the trench and separated from the region of semiconductor material by a dielectric region. A Schottky contact region is disposed adjacent the first major surface on opposing sides of the trench structure, the Schottky contact region having an upper surface residing on a second horizontal plane in the cross-sectional view. The dielectric region comprises an uppermost surface and configured such that a major portion of the uppermost surface is disposed above the first horizontal plane in the cross-sectional view. The structure and method provide a semiconductor device with improved performance (e.g., reduced leakage and more stable breakdown voltage) and improved reliability.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20150243501A1

    公开(公告)日：2015-08-27

    申请号：US14472545

    申请日：2014-08-29

    Applicant: Semiconductor Components Industries, LLC

    Inventor： Michael Thomason ,  Mohammed Tanvir Quddus ,  James Morgan ,  Mihir Mudholkar ,  Scott Donaldson ,  Gordon M Grivna

    IPC: H01L21/02 ,  H01L29/872

    CPC classification number: H01L21/28537 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/76883 ,  H01L21/76889 ,  H01L29/401 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66143 ,  H01L29/8725

    Abstract: A number of variations may include a method that may include depositing a first layer on a first semiconductor epi layer (epitaxial layer) in an overlying position with respect to at least one trench structure formed in the first semiconductor epi layer. The first layer may include a first metal and a second metal. A second layer may comprise a material constructed and arranged to scavenge silicon migrating from the first semiconductor epi layer during annealing may be deposited over the first layer. The first semiconductor epi layer may be subjected to at least a first annealing act to provide a first structure. At least a portion of the first structure may be stripped to remove any of the first layer not reacted with silicon to form a silicide during the first annealing act.

    Abstract translation: 许多变型可以包括一种方法，其可以包括相对于形成在第一半导体外延层中的至少一个沟槽结构，在覆盖位置的第一半导体外延层（外延层）上沉积第一层。 第一层可以包括第一金属和第二金属。 第二层可以包括构造和布置为清除在退火期间从第一半导体外延层迁移的硅的材料可以沉积在第一层上。 可以对第一半导体外延层进行至少第一退火动作以提供第一结构。 可以剥离第一结构的至少一部分以去除在第一退火过程中不与硅反应形成硅化物的任何第一层。

    Method of manufacturing a semiconductor component
    7.
    发明授权
    Method of manufacturing a semiconductor component 有权

    公开(公告)号：US10700219B1

    公开(公告)日：2020-06-30

    申请号：US16789499

    申请日：2020-02-13

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Jefferson W. Hall

    IPC: H01L29/872 ,  H01L29/06 ,  H01L29/47 ,  H01L27/07 ,  H01L27/095 ,  H01L29/66 ,  H01L27/02

    Abstract: A method for manufacturing a semiconductor component includes forming first mesa and second mesa structures from a semiconductor material by etching trenches into the semiconductor material. A doped region having a multi-concentration dopant profile is formed in at least the first mesa structure and doped polysilicon is formed in the trenches. The trenches are formed in a geometric pattern. A contact having three contact types is formed, wherein a first contact type is formed to the first mesa structure, a second contact type is formed to the second mesa structure, and a third contact type is formed to the doped polysilicon in the trenches. The first contact type has electrical properties between a conventional Schottky contact and a conventional Ohmic contact without being a conventional Schottky contact or a conventional Ohmic contact, the second contact type is a Schottky contact, the third contact type is an Ohmic contract.

    Termination structure for insulated gate semiconductor device and method
    8.
    发明授权
    Termination structure for insulated gate semiconductor device and method 有权

    公开(公告)号：US10566466B2

    公开(公告)日：2020-02-18

    申请号：US16396446

    申请日：2019-04-26

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Mohammed Tanvir Quddus ,  Mihir Mudholkar ,  Zia Hossain

    IPC: H01L29/78 ,  H01L29/872 ,  H01L29/40 ,  H01L29/06

    Abstract: A semiconductor device structure includes a region of semiconductor material having an active region and a termination region. An active structure is disposed in the active region and a termination structure is disposed in the termination region. In one embodiment, the termination structure includes a termination trench and a conductive structure within the termination trench and electrically isolated from the region of semiconductor material by a dielectric structure. A dielectric layer is disposed to overlap the termination trench to provide the termination structure as a floating structure. A Schottky contact region is disposed within the active region. A conductive layer is electrically connected to the Schottky contact region and the first conductive layer extends onto a surface of the dielectric layer and laterally overlaps at least a portion of the termination trench.

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