公开(公告)号：US09818749B2

公开(公告)日：2017-11-14

申请号：US15096368

申请日：2016-04-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Masami Endo

IPC: H03K3/356 ,  H01L27/105 ,  G11C11/24 ,  H01L27/108 ,  H01L29/26 ,  G11C19/18 ,  G06F1/32 ,  G11C14/00 ,  H01L49/02 ,  H01L29/24 ,  H01L29/786 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

公开(公告)号：US09735179B2

公开(公告)日：2017-08-15

申请号：US14632282

申请日：2015-02-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami Endo ,  Kazuaki Ohshima

IPC: H01L27/12 ,  H01L29/786 ,  G09G3/36 ,  H01L49/02

CPC classification number: H01L27/1225 ,  G09G3/3648 ,  G09G2300/043 ,  G09G2300/0819 ,  G09G2320/0214 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/7869

Abstract: A semiconductor circuit capable of controlling and holding the threshold voltage of a transistor at an optimal level and a driving method thereof are disclosed. A storage device, a display device, or an electronic device including the semiconductor circuit is also provided. The semiconductor circuit comprises a diode and a first capacitor provided in a node to which a transistor to be controlled is connected through its back gate. This structure allows the application of desired voltage to the back gate so that the threshold voltage of the transistor is controlled at an optimal level and can be held for a long time. A second capacitor connected in parallel with the diode is optionally provided so that the voltage of the node can be changed temporarily.

公开(公告)号：US09344009B2

公开(公告)日：2016-05-17

申请号：US14330081

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami Endo

IPC: H02M7/538 ,  H02M7/5387 ,  B60L15/00

CPC classification number: H02M7/5387 ,  B60L15/007 ,  H02M7/53871 ,  Y02T10/645

Abstract: An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal.

Abstract translation: 目的是通过全桥逆变器电路的控制电路来减少逆变器电路的输出信号的失真，这是由于控制包括在内部的高侧晶体管和低侧晶体管的低侧晶体管的开关导致的误差 第一半桥电路和第二半桥电路。 控制包括在第一半桥电路和第二半桥电路中的高侧晶体管和低侧晶体管的ON / OFF的信号的脉冲宽度减小，即信号的占空比减小 。 这导致高侧晶体管和低侧晶体管导通的短路周期的减少，从而减少信号中的失真。

公开(公告)号：US08891286B2

公开(公告)日：2014-11-18

申请号：US14257050

申请日：2014-04-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami Endo ,  Takuro Ohmaru

IPC: G11C11/24 ,  G11C11/00 ,  G11C11/34 ,  G11C8/00 ,  H03K3/356 ,  H03K21/40

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K21/023 ,  H03K21/403

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract translation: 提供一种可以切换到静止状态并且可以从静止状态快速返回的集成电路。 提供一种能够在不降低运行速度的情况下降低功耗的集成电路。 提供了一种用于驱动集成电路的方法。 集成电路包括第一触发器和包括非易失性存储器电路的第二触发器。 在提供电力的操作状态下，第一触发器保持数据。 在停止供电的静止状态下，第二触发器保持数据。 在从操作状态转变到静止状态时，数据从第一触发器传送到第二触发器。 从静止状态返回到工作状态时，数据从第二触发器传送到第一触发器。

公开(公告)号：US09767862B2

公开(公告)日：2017-09-19

申请号：US15291145

申请日：2016-10-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami Endo

IPC: G11C14/00 ,  G11C7/06 ,  G11C19/18 ,  G11C19/28 ,  G11C7/12 ,  G11C16/04

CPC classification number: G11C7/06 ,  G11C7/12 ,  G11C14/0054 ,  G11C16/0441 ,  G11C19/184 ,  G11C19/28

Abstract: A memory element having a novel structure and a signal processing circuit including the memory element are provided. A first circuit, including a first transistor and a second transistor, and a second circuit, including a third transistor and a fourth transistor, are included. A first signal potential and a second signal potential, each corresponding to an input signal, are respectively input to a gate of the second transistor via the first transistor in an on state and to a gate of the fourth transistor via the third transistor in an on state. After that, the first transistor and the third transistor are turned off. The input signal is read out using both the states of the second transistor and the fourth transistor. A transistor including an oxide semiconductor in which a channel is formed can be used for the first transistor and the third transistor.

公开(公告)号：US20150070064A1

公开(公告)日：2015-03-12

申请号：US14541305

申请日：2014-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Endo ,  Takuro Ohmaru

IPC: H03K3/356 ,  H03K3/012

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K21/023 ,  H03K21/403

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract translation: 提供一种可以切换到静止状态并且可以从静止状态快速返回的集成电路。 提供一种能够在不降低运行速度的情况下降低功耗的集成电路。 提供了一种用于驱动集成电路的方法。 集成电路包括第一触发器和包括非易失性存储器电路的第二触发器。 在提供电力的操作状态下，第一触发器保持数据。 在停止供电的静止状态下，第二触发器保持数据。 在从操作状态转变到静止状态时，数据从第一触发器传送到第二触发器。 从静止状态返回到工作状态时，数据从第二触发器传送到第一触发器。

公开(公告)号：US20150048362A1

公开(公告)日：2015-02-19

申请号：US14461564

申请日：2014-08-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Endo

IPC: H01L29/786 ,  H01L27/115

CPC classification number: H01L27/1052 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

Abstract: To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

Abstract translation: 为了提供具有优异的电荷保持特性的半导体器件，使用OS晶体管作为其栅极连接到用于保持电荷的节点的晶体管。 电荷存储在第一电容器中，并且基于所存储的电荷是否被传送到第二电容器来读取用于保持电荷的节点处的数据。 由于发生通过栅极绝缘膜的漏电流的Si晶体管不被用作连接到用于保持电荷的节点的晶体管，所以节点的电荷保持特性得到改善。 此外，半导体器件在数据读取中工作，而不需要与Si晶体管相当的晶体管性能。