公开(公告)号：US09257971B2

公开(公告)日：2016-02-09

申请号：US14541305

申请日：2014-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Endo ,  Takuro Ohmaru

IPC: G11C11/24 ,  G11C7/00 ,  G11C8/00 ,  H03K3/356 ,  H03K21/02 ,  H03K21/40 ,  H03K3/012

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K21/023 ,  H03K21/403

Abstract: A semiconductor device includes a first latch, a second latch and a transistor whose semiconductor layer contains an oxide semiconductor. An input of the first latch is electrically connected to one of a source and a drain of the transistor, an output of the first latch is electrically connected to an input of the second latch, and an output of the second latch is electrically connected to the other of the source or the drain of the transistor.

Abstract translation: 半导体器件包括第一锁存器，第二锁存器和半导体层包含氧化物半导体的晶体管。 第一锁存器的输入电连接到晶体管的源极和漏极中的一个，第一锁存器的输出电连接到第二锁存器的输入，并且第二锁存器的输出电连接到 晶体管的源极或漏极中的另一个。

公开(公告)号：US20150235700A1

公开(公告)日：2015-08-20

申请号：US14702817

申请日：2015-05-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Masami Endo

IPC: G11C14/00 ,  G11C11/24 ,  H01L49/02 ,  H01L29/786 ,  H01L29/24 ,  H01L27/108

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract translation: 提供能够抑制功耗的信号处理电路。 在不向存储元件提供电源电压的期间中，存储在与非易失性存储器相对应的第一存储电路中的数据可以由设置在第二存储电路中的第一电容器保持。 通过使用在氧化物半导体层中形成沟道的晶体管，保持在第一电容器中的信号被保持很长时间。 因此，存储元件也可以在停止供给电源电压的期间保持存储的内容（数据）。 可以将由第一电容器保持的信号转换为与第二晶体管的状态（导通状态或截止状态）对应的信号，并从第二存储电路读取。 因此，可以准确地读取原始信号。

公开(公告)号：US20140321180A1

公开(公告)日：2014-10-30

申请号：US14330081

申请日：2014-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd

Inventor： Masami Endo

IPC: H02M7/5387

CPC classification number: H02M7/5387 ,  B60L15/007 ,  H02M7/53871 ,  Y02T10/645

Abstract: An object is to reduce, with the control circuit of the full-bridge inverter circuit, distortions in an output signal of the inverter circuit resulting from an error in control of the switching of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit. The pulse width of a signal that controls ON/OFF of the high-side transistors and low-side transistors included in the first half-bridge circuit and the second half-bridge circuit is reduced, i.e., the duty cycle of the signal is reduced. This results in a reduction in short-circuit periods during which both the high-side transistor and the low-side transistor are on, thereby reducing distortions in a signal.

Abstract translation: 目的是通过全桥逆变器电路的控制电路来减少逆变器电路的输出信号的失真，这是由于控制包括在内部的高侧晶体管和低侧晶体管的低侧晶体管的开关导致的误差 第一半桥电路和第二半桥电路。 控制包括在第一半桥电路和第二半桥电路中的高侧晶体管和低侧晶体管的ON / OFF的信号的脉冲宽度减小，即信号的占空比减小 。 这导致高侧晶体管和低侧晶体管导通的短路周期的减少，从而减少信号中的失真。

公开(公告)号：US20140226394A1

公开(公告)日：2014-08-14

申请号：US14257050

申请日：2014-04-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Endo ,  Takuro Ohmaru

IPC: H03K3/356 ,  H03K21/40 ,  H03K21/02

CPC classification number: H03K3/356008 ,  H03K3/012 ,  H03K21/023 ,  H03K21/403

Abstract: An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Abstract translation: 提供一种可以切换到静止状态并且可以从静止状态快速返回的集成电路。 提供一种能够在不降低运行速度的情况下降低功耗的集成电路。 提供了一种用于驱动集成电路的方法。 集成电路包括第一触发器和包括非易失性存储器电路的第二触发器。 在提供电力的操作状态下，第一触发器保持数据。 在停止供电的静止状态下，第二触发器保持数据。 在从操作状态转变到静止状态时，数据从第一触发器传送到第二触发器。 从静止状态返回到工作状态时，数据从第二触发器传送到第一触发器。

公开(公告)号：US09024669B2

公开(公告)日：2015-05-05

申请号：US14068217

申请日：2013-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Masami Endo

IPC: H03K3/356 ,  H01L27/108 ,  G11C11/24 ,  H01L29/26

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract translation: 提供能够抑制功耗的信号处理电路。 在不向存储元件提供电源电压的期间中，存储在与非易失性存储器相对应的第一存储电路中的数据可以由设置在第二存储电路中的第一电容器保持。 通过使用在氧化物半导体层中形成沟道的晶体管，保持在第一电容器中的信号被保持很长时间。 因此，存储元件也可以在停止供给电源电压的期间保持存储的内容（数据）。 可以将由第一电容器保持的信号转换为与第二晶体管的状态（导通状态或截止状态）对应的信号，并从第二存储电路读取。 因此，可以准确地读取原始信号。

公开(公告)号：US20140048802A1

公开(公告)日：2014-02-20

申请号：US14068217

申请日：2013-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takuro Ohmaru ,  Masami Endo

IPC: H01L27/108 ,  H01L29/26

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.

Abstract translation: 提供能够抑制功耗的信号处理电路。 在不向存储元件提供电源电压的期间中，存储在与非易失性存储器相对应的第一存储电路中的数据可以由设置在第二存储电路中的第一电容器保持。 通过使用在氧化物半导体层中形成沟道的晶体管，保持在第一电容器中的信号被保持很长时间。 因此，存储元件也可以在停止供给电源电压的期间保持存储的内容（数据）。 可以将由第一电容器保持的信号转换为与第二晶体管的状态（导通状态或截止状态）对应的信号，并从第二存储电路读取。 因此，可以准确地读取原始信号。

公开(公告)号：US10008502B2

公开(公告)日：2018-06-26

申请号：US15497752

申请日：2017-04-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masami Endo

IPC: H01L27/108 ,  H01L29/786 ,  H01L27/1156

CPC classification number: H01L27/10805 ,  H01L27/108 ,  H01L27/10847 ,  H01L27/1085 ,  H01L27/10855 ,  H01L27/10867 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869 ,  H01L29/78696

Abstract: A memory device which stores a large amount of data is provided. The memory device includes a first transistor, a second transistor, a third transistor, a first capacitor, a second capacitor, and first to third wirings. The first transistor includes an oxide semiconductor in a channel formation region, the second transistor includes silicon in a channel formation region, and the third transistor includes silicon in a channel formation region. The first capacitor is provided in the same layer as the first transistor. A region of the second capacitor and a region of the first capacitor overlap with each other. The thickness of a dielectric of the second capacitor is preferably larger than the thickness of a dielectric of the first capacitor.

公开(公告)号：US09847406B2

公开(公告)日：2017-12-19

申请号：US15238933

申请日：2016-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Masami Endo

IPC: H01L29/10 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L27/1156

CPC classification number: H01L29/66969 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/7869

Abstract: A semiconductor device capable of retaining data for a long time is provided. A semiconductor device includes a first transistor including a first insulator, a first oxide semiconductor, a first gate, and a second gate; a second transistor including a second oxide semiconductor, a third gate, and a fourth gate; and a node. The first gate and the second gate overlap with each other with the first oxide semiconductor therebetween. The third gate and the fourth gate overlap with each other with the second oxide semiconductor therebetween. The first oxide semiconductor and the second gate overlap with each other with the first insulator therebetween. One of a source and a drain of the first transistor, the first gate, and the fourth gate are electrically connected to the node. The first insulator is configured to charges.

公开(公告)号：US09608005B2

公开(公告)日：2017-03-28

申请号：US14461564

申请日：2014-08-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masami Endo

IPC: H01L29/04 ,  H01L27/12

CPC classification number: H01L27/1052 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/7869

Abstract: To provide a semiconductor device with excellent charge retention characteristics, an OS transistor is used as a transistor whose gate is connected to a node for retaining charge. Charge is stored in a first capacitor, and data at the node for retaining charge is read based on whether the stored charge is transferred to a second capacitor. Since a Si transistor, in which leakage current through a gate insulating film occurs, is not used as a transistor connected to the node for retaining charge, charge retention characteristics of the node are improved. In addition, the semiconductor device operates in data reading without requiring transistor performance equivalent to that of a Si transistor.

公开(公告)号：US09330759B2

公开(公告)日：2016-05-03

申请号：US14702817

申请日：2015-05-04

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takuro Ohmaru ,  Masami Endo

IPC: H03K3/356 ,  G11C14/00 ,  H01L29/24 ,  H01L27/108 ,  H01L49/02 ,  H01L29/786 ,  G11C11/24

CPC classification number: H01L27/1052 ,  G06F1/3275 ,  G11C11/24 ,  G11C14/0009 ,  G11C19/184 ,  H01L23/5226 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10897 ,  H01L28/20 ,  H01L28/40 ,  H01L29/24 ,  H01L29/26 ,  H01L29/7869 ,  Y02D10/13 ,  Y02D10/14

Abstract: A signal processing circuit whose power consumption can be suppressed is provided. In a period during which a power supply voltage is not supplied to a storage element, data stored in a first storage circuit corresponding to a nonvolatile memory can be held by a first capacitor provided in a second storage circuit. With the use of a transistor in which a channel is formed in an oxide semiconductor layer, a signal held in the first capacitor is held for a long time. The storage element can accordingly hold the stored content (data) also in a period during which the supply of the power supply voltage is stopped. A signal held by the first capacitor can be converted into the one corresponding to the state (the on state or off state) of the second transistor and read from the second storage circuit. Consequently, an original signal can be accurately read.