公开(公告)号：US20240055533A1

公开(公告)日：2024-02-15

申请号：US18383526

申请日：2023-10-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

公开(公告)号：US20180122958A1

公开(公告)日：2018-05-03

申请号：US15846518

申请日：2017-12-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786 ,  H01L29/24 ,  H01L29/04 ,  H01L29/66 ,  H01L27/12 ,  H01L29/12

CPC classification number: H01L29/7869 ,  H01L21/2636 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/12 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78696

Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

公开(公告)号：US20150050775A1

公开(公告)日：2015-02-19

申请号：US14529525

申请日：2014-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Ryosuke WATANABE ,  Suzunosuke HIRAISHI ,  Junichiro SAKATA

IPC: H01L21/477 ,  H01L29/66

CPC classification number: H01L21/477 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/7869

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.

Abstract translation: 目的在于提供一种具有稳定的电气特性和高可靠性的氧化物半导体的半导体装置。 在包括氧化物半导体层的底栅晶体管的制造工艺中，在氧化物气氛中进行热处理，在真空中进行热处理，依次进行氧化物半导体层的脱水或脱氢。 此外，与热处理同时进行具有短波长的光的照射，由此促进氢，OH等的消除。 包括通过这种热处理进行脱水或脱氢处理的氧化物半导体层的晶体管具有改善的稳定性，从而抑制了由于光照射或偏压温度应力（BT）测试而导致的晶体管的电特性的变化。

公开(公告)号：US20150041801A1

公开(公告)日：2015-02-12

申请号：US14447875

申请日：2014-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Takuya HIROHASHI ,  Masahiro TAKAHASHI ,  Motoki NAKASHIMA ,  Ryosuke WATANABE ,  Masashi TSUBUKU

IPC: H01L29/792 ,  H01L29/24

CPC classification number: H01L29/792 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66969 ,  H01L29/7869

Abstract: A semiconductor device includes a semiconductor layer, a gate electrode overlapping with the semiconductor layer, a first gate insulating layer between the semiconductor layer and the gate electrode, and a second gate insulating layer between the first gate insulating layer and the gate electrode. The first gate insulating layer includes an oxide in which the nitrogen content is lower than or equal to 5 at. %, and the second gate insulating layer includes charge trap states.

Abstract translation: 半导体器件包括半导体层，与半导体层重叠的栅极电极，在半导体层和栅电极之间的第一栅极绝缘层，以及位于第一栅极绝缘层和栅电极之间的第二栅极绝缘层。 第一栅极绝缘层包括其中氮含量低于或等于5at的氧化物。 ％，第二栅极绝缘层包括电荷陷阱状态。

公开(公告)号：US20210384356A1

公开(公告)日：2021-12-09

申请号：US17349974

申请日：2021-06-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04

Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

公开(公告)号：US20190147312A1

公开(公告)日：2019-05-16

申请号：US16248349

申请日：2019-01-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryosuke WATANABE ,  Naoto KUSUMOTO ,  Osamu NAKAMURA

IPC: G06K19/077 ,  H01L21/56

Abstract: Thin film integrated circuits are peeled from a substrate and the peeled thin film integrated circuits are sealed, efficiently in order to improve manufacturing yields. The present invention provides laminating system comprising transporting means for transporting a substrate provided with a plurality of thin film integrated circuits; first peeling means for bonding first surfaces of the thin film integrated circuits to a first sheet member to peel the thin film integrated circuits from the substrate; second peeling means for bonding second surfaces of the thin film integrated circuits to a second sheet member to peel the thin film integrated circuits from the first sheet member; and sealing means for interposing the thin film integrated circuits between the second sheet member and a third sheet member to seal the thin film integrated circuit with the second sheet member and the third sheet member.

公开(公告)号：US20180226510A1

公开(公告)日：2018-08-09

申请号：US15942957

申请日：2018-04-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696

Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.

公开(公告)号：US20160218226A1

公开(公告)日：2016-07-28

申请号：US15090937

申请日：2016-04-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masayuki SAKAKURA ,  Ryosuke WATANABE ,  Junichiro SAKATA ,  Kengo AKIMOTO ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Hideyuki KISHIDA

IPC: H01L29/786 ,  H01L29/04 ,  H01L29/24

CPC classification number: H01L29/78696 ,  H01L21/2636 ,  H01L27/1225 ,  H01L29/04 ,  H01L29/045 ,  H01L29/12 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/7869

Abstract: It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

公开(公告)号：US20140220745A1

公开(公告)日：2014-08-07

申请号：US14217519

申请日：2014-03-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryosuke WATANABE ,  Hidekazu TAKAHASHI ,  Takuya TSURUME

IPC: H01L21/56

CPC classification number: H01L21/56 ,  B32B37/20 ,  B32B2305/342 ,  B42D25/45 ,  B42D2033/46 ,  G06K19/07718 ,  G06K19/07749 ,  G06K19/0775 ,  H01L21/67126 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6835 ,  H01L27/1214 ,  H01L27/1266 ,  H01L2221/68318 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2924/0002 ,  Y10T156/1089 ,  Y10T156/1093 ,  Y10T156/1712 ,  H01L2924/00

Abstract: It is an object of the invention to improve the production efficiency in sealing a thin film integrated circuit and to prevent the damage and break. Further, it is another object of the invention to prevent a thin film integrated circuit from being damaged in shipment and to make it easier to handle the thin film integrated circuit. The invention provides a laminating system in which rollers are used for supplying a substrate for sealing, receiving IC chips, separating, and sealing. The separation, sealing, and reception of a plurality of thin film integrated circuits can be carried out continuously by rotating the rollers; thus, the production efficiency can be extremely improved. Further, the thin film integrated circuits can be easily sealed since a pair of rollers opposite to each other is used.

Abstract translation: 本发明的目的是提高密封薄膜集成电路的生产效率并防止损坏和断裂。 此外，本发明的另一个目的是防止薄膜集成电路在运输中受损，并且使得更容易处理薄膜集成电路。 本发明提供了一种层压系统，其中辊子用于供应用于密封的基板，接收IC芯片，分离和密封。 通过旋转辊可以连续地进行多个薄膜集成电路的分离，密封和接收; 从而可以极大地提高生产效率。 此外，由于使用了彼此相对的一对辊，所以能够容易地密封薄膜集成电路。