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公开(公告)号：US11081150B2
公开(公告)日：2021-08-03
申请号：US16439452
申请日：2019-06-12
Applicant: SK hynix Inc.
Inventor： Sang Gu Jo , Donggun Kim , Yong Ju Kim , Do-Sun Hong
Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.
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公开(公告)号：US10777274B2
公开(公告)日：2020-09-15
申请号：US16029088
申请日：2018-07-06
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Jung-Hyun Kwon , Won-Gyu Shin , Do-Sun Hong
Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.
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公开(公告)号：US10679691B2
公开(公告)日：2020-06-09
申请号：US16203350
申请日：2018-11-28
Applicant: SK hynix Inc.
Inventor： Seung Gyu Jeong , Do-Sun Hong , Su Hae Woo , Chang Soo Ha
IPC: G11C16/04 , G11C11/4072 , G11C11/408 , G11C8/04 , G11C16/08 , G11C16/24 , G11C8/18
Abstract: A semiconductor system may include a memory device and a controller. The memory device may include a plurality of decks. Each of the decks may include word lines and bit lines alternately stacked. The controller may control an operation for data of the decks included in the memory device. The controller may include a counting circuit block for counting access numbers of the word lines and the bit lines. The counting circuit block may include a plurality of x-counting blocks corresponding to the word lines that are stacked a plurality of y-counting blocks corresponding to the bit lines that are stacked. The x-counting blocks may count access numbers of selected word lines in accordance with a selection signal of a corresponding deck among the decks. The y-counting block may count access numbers of selected bit lines in accordance with the selection signal of the corresponding deck.
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14.发明授权公开(公告)号：US10607694B2
公开(公告)日：2020-03-31
申请号：US16124882
申请日：2018-09-07
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Won-Gyu Shin , Jung-Hyun Kwon , Do-Sun Hong
Abstract: A memory system includes a memory device comprising first to Nth memory regions, wherein N is a natural number equal to or more than 2, and a memory controller suitable for checking numbers of first logic level data which are contained in first to Nth data groups to be written to the memory device, respectively, and writing the first to Nth data groups to the first to Nth memory regions in order based on the checked numbers.
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公开(公告)号：US10198184B2
公开(公告)日：2019-02-05
申请号：US15434784
申请日：2017-02-16
Applicant: SK hynix Inc.
Inventor： Do-Sun Hong , Donggun Kim , Yong Ju Kim , Sang Gu Jo
Abstract: A resistance variable memory apparatus may include a memory circuit configured to include a plurality of blocks, each including a plurality of memory cells. The resistance variable memory apparatus may include a disturbance preventing circuit configured to be driven based on a counting signal corresponding to the number of write access for each of the plurality of blocks, a write command, and an address signal and to allow scrubbing to be performed on a memory cell having a preset scrubbing condition when the counting signal satisfied with the scrubbing condition is output based on the scribing condition according to a physical position of the memory cell in the block.
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Patent Agency Ranking
公开(公告)号：US11355190B2
公开(公告)日：2022-06-07
申请号：US16993787
申请日：2020-08-14
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Jung-Hyun Kwon , Won-Gyu Shin , Do-Sun Hong
Abstract: A semiconductor memory system including a resistive variable memory device and a driving method thereof are provided. The semiconductor memory system includes a memory controller including a scheduler configured to determine a generation period of a write command; a memory device including a memory cell array, the memory device being configured to write data input from the memory controller in the memory cell array in response to the write command; and a data determination circuit configured to output a change signal to the scheduler when all logic levels of the input data are equal to each other, the scheduler changing the generation period of the write command in response to the change signal.
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公开(公告)号：US10776262B2
公开(公告)日：2020-09-15
申请号：US16169835
申请日：2018-10-24
Applicant: SK hynix Inc.
Inventor： Do-Sun Hong , Jung Hyun Kwon , Won Gyu Shin , Seung Gyu Jeong
Abstract: A memory system may include a nonvolatile memory device and a wear leveling unit. The nonvolatile memory device includes a plurality of memory blocks. The wear leveling unit may be configured to intermittently increase an accumulative access count of a memory block among the memory blocks by a predetermined value, decide a wear level of the memory block based on the accumulative access count whenever the accumulative access count is increased, set the memory block to a hot block based on the wear level, and perform a hot block management operation on the hot block. The wear leveling unit may increase the accumulative access count in response to an access count reaching a predetermined value. The accumulative access count may be stored in the nonvolatile memory device, and the access count may be stored in a volatile memory device.
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公开(公告)号：US10482961B2
公开(公告)日：2019-11-19
申请号：US16007598
申请日：2018-06-13
Applicant: SK hynix Inc.
Inventor： Seung-Gyu Jeong , Jung-Hyun Kwon , Do-Sun Hong , Won-Gyu Shin
Abstract: A memory system includes a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit, wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells.
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公开(公告)号：US10445005B2
公开(公告)日：2019-10-15
申请号：US15726460
申请日：2017-10-06
Applicant: SK hynix Inc.
Inventor： Do-Sun Hong , Yong-Ju Kim , Dong-Gun Kim
Abstract: A memory system includes a wear-leveling module detecting a hot memory block among a plurality of memory blocks based on the number of times write operations are performed on each of the memory blocks, and moving data from the hot memory block to a spare memory block, a counting unit counting the number of data movement from the hot memory block to the spare memory block, on each of memory regions formed by grouping the plurality of memory blocks, and output data movement counts, a first detection unit selecting one from the plurality of memory regions based on the data movement count, and detecting a cold memory block among memory blocks included in the selected memory region, and a management unit moving data from the cold memory block to the hot memory block, and managing the cold memory block as the spare memory block.
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公开(公告)号：US10360950B2
公开(公告)日：2019-07-23
申请号：US15439186
申请日：2017-02-22
Applicant: SK hynix Inc.
Inventor： Sang Gu Jo , Donggun Kim , Yong Ju Kim , Do-Sun Hong
Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.
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