公开(公告)号：US09712152B2

公开(公告)日：2017-07-18

申请号：US14862240

申请日：2015-09-23

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto

IPC: H03K3/01 ,  H03K17/16 ,  H03K19/00

CPC classification number: H03K17/162 ,  H03K19/0016 ,  H03K2217/0018 ,  H03K2217/0036

Abstract: A circuit for controlling power supply includes a first switch situated between a first power supply and a first node coupled to a circuit block, a second switch situated between a second power supply having a voltage value different than the first power supply and a second node coupled to a back gate of a transistor of the circuit block, a third switch situated between the first node and the second node, and a control unit configured to place the second switch in an “on” state and the third switch in an “off” state during an “on” state of the first switch, and to place the second switch in an “off” state and the third switch in an “on” state during an “off” state of the first switch.

公开(公告)号：US20210020571A1

公开(公告)日：2021-01-21

申请号：US17063452

申请日：2020-10-05

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/78 ,  H03K17/687

Abstract: A power switch cell using vertical nanowire (VNW) FETs includes a switch element configured to be capable of switching between electrical connection and disconnection between a global power interconnect and a local power interconnect. The switch element is constituted by at least one VNW FET. The top electrode of the VNW FET constituting the switch element is connected with the global power interconnect.

公开(公告)号：US20180315743A1

公开(公告)日：2018-11-01

申请号：US15953899

申请日：2018-04-16

Applicant: Socionext Inc.

Inventor： Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/02 ,  H03K17/16 ,  H01L23/528 ,  H01L27/088 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L27/0207 ,  H01L21/823871 ,  H01L21/823892 ,  H01L23/5286 ,  H01L27/088 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/785 ,  H01L2027/11875 ,  H01L2027/11881 ,  H03K17/161 ,  H03K19/0016

Abstract: A semiconductor device includes a first circuit, a second circuit, a first power supply line, a second power supply line coupled to the first circuit, a third power supply line, a fourth power supply line coupled to the second circuit, a first switch circuit including a first switch transistor and a well tap, the first switch transistor including one source or drain end coupled to the first power supply line and another source or drain end coupled to the second power supply line, the well tap being electrically coupled to the second power supply line, and a second switch circuit including a second switch transistor including one source or drain end coupled to the third power supply line and another source or drain end coupled to the fourth power supply line, the second switch circuit including no well tap electrically coupled to the fourth power supply line.

公开(公告)号：US09692415B2

公开(公告)日：2017-06-27

申请号：US14797885

申请日：2015-07-13

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto

IPC: H03K19/00 ,  H03K19/0185 ,  H03K17/693

CPC classification number: H03K19/0013 ,  H03K17/693 ,  H03K19/0016 ,  H03K19/018521

Abstract: A semiconductor device includes a first power supply node and a second power supply node having a voltage value higher than the first power supply node. A first switch interrupts a power supplied from the first power supply node to a first circuit node. A second switch interrupts a power supplied from the second power supply node to a second circuit node. A driver drives the second switch by a third switch being driven. The third switch is connected between the second power supply node and the first circuit node. A controller outputs a control signal to drive the first and third switches.

公开(公告)号：US12284828B2

公开(公告)日：2025-04-22

申请号：US17829341

申请日：2022-05-31

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H10D84/90

Abstract: A semiconductor device includes a first chip including a substrate and a first wiring layer formed on a first surface of the substrate; and a second wiring layer formed on a second surface of the substrate opposite to the first surface of the substrate. The second wiring layer includes a first power line to which a first power potential is applied; a second power line to which a second power potential is applied; a third power line to which a third power potential is applied; a first switch connected between the first power line and the second power line; and a second switch provided on one of the first power line or the third power line. The first chip includes a first circuit provided between the first power line and the third power line.

公开(公告)号：US12119301B2

公开(公告)日：2024-10-15

申请号：US17716299

申请日：2022-04-08

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Atsushi Okamoto ,  Hirotaka Takeno

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L23/5226

Abstract: A semiconductor device includes a chip that includes a substrate and a first interconnection layer on a surface of the substrate; and a second interconnection layer on another surface opposite to the surface of the substrate. The second interconnection layer includes a first power line having a first power potential, a second power line having a second power potential, and a switch between the first power line and the second power line. The chip includes a first grounding line, a third power line having the second power potential, a first region having the first grounding line and the third power line, a second grounding line, a fourth power line having the first power potential, and a second region having the second grounding line and the fourth power line. In plan view, the switch is between the first region and the second region.

公开(公告)号：US12087735B2

公开(公告)日：2024-09-10

申请号：US17210743

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Hirotaka Takeno ,  Wenzhen Wang ,  Atsushi Okamoto

IPC: H01L25/065 ,  G11C5/14 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L27/0207 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06544

Abstract: A semiconductor device includes a first semiconductor chip, and a second semiconductor chip, wherein the first semiconductor chip includes a substrate including a first principal surface facing the second semiconductor chip and a second principal surface opposite to the first principal surface, a first power supply line and a second power supply line arranged on the second principal surface of the substrate, a power supply switch circuit arranged electrically between the first power supply line and the second power supply line, a first via arranged in the substrate to extend from the first power supply line to the first principal surface, and a second via arranged in the substrate to extend from the second power supply line to the first principal surface, wherein the second semiconductor chip includes a third power supply line connected to the first via, and a fourth power supply line connected to the second via.

公开(公告)号：US12046598B2

公开(公告)日：2024-07-23

申请号：US17507567

申请日：2021-10-21

Applicant: Socionext Inc.

Inventor： Wenzhen Wang ,  Hirotaka Takeno ,  Atsushi Okamoto

IPC: H01L27/092 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/0922 ,  H01L23/5286 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a first power supply line, a second power supply line, a first ground line, a switch circuit connected to the first and the second power supply line, and a switch control circuit connected to the first ground line and the first power supply line. The switch circuit includes a first and a second transistor of a first conductive type. A first gate electrode of the first transistor is connected to a second gate electrode of the second transistor. The switch control circuit includes a third transistor of a second conductive type, and a fourth transistor of a third conductive type. A third gate electrode of the third transistor is connected to a fourth gate electrode of the fourth transistor. A semiconductor device includes a signal line that electrically connects a connection point between the third and fourth transistor to the first and second gate electrode.

公开(公告)号：US11799471B2

公开(公告)日：2023-10-24

申请号：US18069084

申请日：2022-12-20

Applicant: Socionext Inc.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Junji Iwahori

IPC: H03K17/00 ,  H03K17/16 ,  H03K17/687 ,  H03K19/00

CPC classification number: H03K17/161 ,  H03K17/6871 ,  H03K19/0008

Abstract: A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

公开(公告)号：US11626386B2

公开(公告)日：2023-04-11

申请号：US17206257

申请日：2021-03-19

Applicant: SOCIONEXT INC.

Inventor： Atsushi Okamoto ,  Hirotaka Takeno ,  Wenzhen Wang

IPC: H01L23/50 ,  H01L25/065 ,  H01L23/538 ,  H01L27/088

Abstract: A semiconductor integrated circuit device includes first and second semiconductor chips stacked one on top of the other. First power supply lines in the first semiconductor chip are connected with second power supply lines in the second semiconductor chip through a plurality of first vias. The directions in which the first power supply lines and the second power supply lines extend are orthogonal to each other.