公开(公告)号：US20250047279A1

公开(公告)日：2025-02-06

申请号：US18920681

申请日：2024-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Vaibhav GARG ,  Abhishek JAIN ,  Anand KUMAR

IPC: H03K17/687 ,  H03K17/693 ,  H03K19/017

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

公开(公告)号：US20240364357A1

公开(公告)日：2024-10-31

申请号：US18592210

申请日：2024-02-29

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek JAIN ,  Anand KUMAR

IPC: H03M3/00 ,  H03B5/24

CPC classification number: H03M3/30 ,  H03B5/24

Abstract: Various examples in accordance with the present disclosure provide example methods, systems, and apparatuses that may calibrate a resistor-capacitor (RC) circuit.

公开(公告)号：US20220352896A1

公开(公告)日：2022-11-03

申请号：US17863708

申请日：2022-07-13

Applicant: STMicroelectronics International N.V.

Inventor： Gagan MIDHA ,  Kallol CHATTERJEE ,  Anand KUMAR ,  Ankit GUPTA

IPC: H03L7/089 ,  H03L7/099 ,  H03L7/093 ,  H03L7/197

Abstract: A phase lock loop (PLL) includes an input comparison circuit configured to compare a reference signal to a divided feedback signal and generate at least one charge pump control signal based thereupon. A charge pump generates a charge pump output signal in response to the at least one charge pump control signal. A loop filter is coupled to receive and filter the charge pump output signal to produce an oscillator control signal. An oscillator generates an output signal in response to the oscillator control signal, with the output signal divided by a divisor using divider circuitry to produce the divided feedback signal. Divisor generation circuitry is configured to change the divisor over time so that a frequency of the divided feedback signal changes from a first frequency to a second frequency over time.

公开(公告)号：US20200235702A1

公开(公告)日：2020-07-23

申请号：US16703250

申请日：2019-12-04

Applicant: STMicroelectronics International N.V.

Inventor： Anand KUMAR ,  Nitin JAIN

IPC: H03B5/36 ,  H03B5/06

Abstract: A clock signal is generated with an oscillator. A crystal oscillator core within the oscillator circuit is switched on to produce first and second oscillation signals that are approximately opposite in phase. When a difference between a voltage of the first oscillation signal and a voltage of the second oscillation signal exceeds an upper threshold range, the crystal oscillator core is switched off. When the difference between the voltage of the first oscillation signal and the voltage of the second oscillation signal falls below the upper threshold range, the crystal oscillator core is switched back on. This operation is repeated so as to produce the clock signal.

公开(公告)号：US20160111534A1

公开(公告)日：2016-04-21

申请号：US14985264

申请日：2015-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anand KUMAR ,  Ankit AGRAWAL

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/762 ,  H01L29/51 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L29/7831 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/78648

Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.