公开(公告)号：US11094354B2

公开(公告)日：2021-08-17

申请号：US17015271

申请日：2020-09-09

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh ,  Vivek Tripathi

IPC: G11C7/10 ,  H03L7/107 ,  G11C7/22 ,  H03M1/00 ,  G11C7/04

Abstract: A quantizer generates a thermometer coded signal from an analog voltage signal. Data weighted averaging (DWA) of the thermometer coded signal is accomplished by controlling the operation of a crossbar switch controlled by a switch control signal to generate an output DWA signal. The output DWA signal is latched to generate a latched output DWA signal which is processed along with bits of the thermometer coded input signal in feedback loop to generate the switch control signal. The latching of the output DWA signal is performed in an input register of a digital-to-analog converter which operates to convert the latched output DWA signal to a feedback analog voltage from which the analog voltage signal is generated. The switch control signal specifies a bit location for a beginning logic transition of the output DWA signal cycle based on detection of an ending logic transition of the latched DWA signal.

公开(公告)号：US10050606B2

公开(公告)日：2018-08-14

申请号：US15632202

申请日：2017-06-23

Applicant: STMicroelectronics International N.V.

Inventor： Neha Bhargava ,  Ankur Bal

IPC: H03H17/02 ,  H03H21/00

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

公开(公告)号：US20160182014A1

公开(公告)日：2016-06-23

申请号：US14573055

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Neha Bhargava ,  Ankur Bal

IPC: H03H17/02

CPC classification number: H03H17/0664 ,  H03H17/0275 ,  H03H2017/0245

Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract translation: 一种多相位抽取FIR滤波器装置，包括：模积分器电路，被配置为集成输入采样并提供集成的输入采样; 以及多相FIR滤波器电路，被配置为处理所述积分输入样本，所述多相FIR滤波器电路包括多个乘法器累加器电路，每个乘法器累加器电路被配置为累积系数乘积和相应的积分信号采样，其中每个乘法器累加器电路接收子集 的FIR滤波器系数，其中FIR滤波器系数被导出为原始滤波器系数的第n个差，其中n是积分器电路中的积分器的数量，并且其中FIR滤波器电路被配置为通过模运算执行计算操作。

公开(公告)号：US12093193B2

公开(公告)日：2024-09-17

申请号：US17067967

申请日：2020-10-12

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F13/16 ,  G06F7/487 ,  G06F9/30 ,  G06F17/16

CPC classification number: G06F13/1668 ,  G06F7/4876 ,  G06F9/3001 ,  G06F9/30021 ,  G06F17/16

Abstract: Individual bits of a K bit unary data word, wherein K is greater than one, are applied to K polyphase finite impulse response filter circuits. Each polyphase finite impulse response filter circuit receives a different bit and operates with a single bit precision to generate from each received bit a filtered output data word. A gain adjustment is applied by a gain stage circuit to each filtered output data word to generate a corresponding gain adjusted output data word. The gain adjusted output data words from the gain stage circuits are summed to generate an output data word. The unary data word may be output from a source such as a data encoder or a quantizer.

公开(公告)号：US11989148B2

公开(公告)日：2024-05-21

申请号：US17548101

申请日：2021-12-10

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F13/42 ,  G06F1/06 ,  G06F1/08 ,  H03K3/037

CPC classification number: G06F13/42 ,  G06F1/06 ,  G06F1/08 ,  H03K3/037

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem include a clock edge selector configured to determine a phase difference between the first clock signal and the second clock signal and to select, based on the phase difference, either a rising edge or a falling edge of the second clock signal to control output of data from the first subsystem to the second subsystem.

公开(公告)号：US11979167B2

公开(公告)日：2024-05-07

申请号：US17876263

申请日：2022-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Sharad Gupta ,  Ankur Bal

IPC: H03M1/06

CPC classification number: H03M1/0665

Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

公开(公告)号：US11921537B2

公开(公告)日：2024-03-05

申请号：US17821398

申请日：2022-08-22

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Jeet Narayan Tiwari

IPC: G06F1/08 ,  H03K3/037 ,  H03K5/26 ,  H03K19/20 ,  H03M7/16

CPC classification number: G06F1/08 ,  H03K3/037 ,  H03K5/26 ,  H03K19/20 ,  H03M7/16

Abstract: An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.

公开(公告)号：US11901919B2

公开(公告)日：2024-02-13

申请号：US17723225

申请日：2022-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Abhishek Jain ,  Sharad Gupta

IPC: H03M3/00

CPC classification number: H03M3/378 ,  H03M3/46 ,  H03M3/496

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US11552646B2

公开(公告)日：2023-01-10

申请号：US17354126

申请日：2021-06-22

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Vikram Singh

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

公开(公告)号：US11092993B2

公开(公告)日：2021-08-17

申请号：US16437705

申请日：2019-06-11

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Rupesh Singh

IPC: G06F1/02 ,  H03K4/02 ,  H03K3/80

Abstract: A recursive digital sinusoid generator generates recursive values used in the production of a digital sinusoid output. The recursive values are generated at a first frequency. A sinusoid value generator generates replacement values at a second frequency, wherein the second frequency is less than the first frequency. The generated recursive values are periodically replaced with the generated replacement values without interrupting production of the digital sinusoid output at the first frequency. This periodic replacement effectively corrects for a finite precision error which accumulates in the recursive values over time.