公开(公告)号：US20030235092A1

公开(公告)日：2003-12-25

申请号：US10423845

申请日：2003-04-24

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Aldo Losavio

IPC: G11C007/00

CPC classification number: G11C29/808

Abstract: The self-repair method for a nonvolatile memory intervenes at the end of an operation of modification, selected between programming and erasing, in the event of detection of just one non-functioning cell, and carries out redundancy of the non-functioning cell. To this end, the memory array is divided into a basic portion, formed by a plurality of memory cells storing basic data, and into a in-the-field redundancy portion, said in-the-field redundancy portion being designed to store redundancy data including a correct content of the non-functioning cell, the address of the non-functioning cell, and an activated redundancy flag. The redundancy is activated only after applying a preset maximum number of modification pulses and uses a purposely designed redundancy replacement circuit and a purposely designed redundancy data verification circuit.

Abstract translation: 在检测到仅一个非功能单元的情况下，非易失性存储器的自修复方法在编程和擦除之间选择的修改操作结束时进行干预，并且执行非功能单元的冗余。 为此，存储器阵列被划分为由存储基本数据的多个存储单元形成的基本部分，并且进入现场冗余部分，所述现场冗余部分被设计为存储冗余数据 包括非正常单元的正确内容，非功能单元的地址和激活的冗余标志。 冗余仅在应用预设的最大数量的修改脉冲之后被激活，并且使用专门设计的冗余替换电路和专门设计的冗余数据验证电路。

公开(公告)号：US20030231532A1

公开(公告)日：2003-12-18

申请号：US10417416

申请日：2003-04-15

Applicant: STMicroelectronics S.r.l

Inventor： Rino Micheloni ,  Aldo Losavio

IPC: G11C029/00

CPC classification number: G06F11/1068

Abstract: The method for using a nonvolatile memory having a plurality of cells, each of which stores a datum, is based upon the steps of performing an modification operation of erasing/programming the data of the memory; verifying the correctness of the data of the memory cells; and, if the step of verifying has revealed at least one incorrect datum, correcting on-the-field the incorrect datum, using an error correcting code. The verification of the correctness of the data is performed by determining the number of memory cells storing an incorrect datum; if the number of memory cells storing the incorrect datum is less than or equal to a threshold, the erroneous datum is corrected by the error correction code; otherwise, new erasing/programming pulses are supplied.

Abstract translation: 使用具有存储数据的多个单元的非易失性存储器的方法基于执行擦除/编程存储器的数据的修改操作的步骤; 验证存储器单元的数据的正确性; 并且如果验证步骤已经显示出至少一个不正确的数据，则使用错误校正码对现场校正不正确的数据进行校正。 通过确定存储不正确数据的存储单元的数量来执行数据的正确性的验证; 如果存储不正确的数据的存储单元的数量小于或等于阈值，则错误校正码校正错误的数据; 否则，将提供新的擦除/编程脉冲。

公开(公告)号：US20020192892A1

公开(公告)日：2002-12-19

申请号：US10133231

申请日：2002-04-26

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: H01L021/8238

CPC classification number: G11C11/5621 ,  G11C5/147 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26 ,  G11C2211/5634

Abstract: The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second reference circuit respectively connected to said first and said second memory cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage; and a voltage divider having a first connection node and a second connection node respectively connected to the output terminals of the first reference circuit and of the second reference circuit to receive, respectively, the first reference voltage and the second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.

Abstract translation: 用于产生用于读取多电平存储器单元的参考电压的电路包括：分别具有第一参考编程电平和第二参考编程电平的第一存储单元和第二存储单元; 分别连接到所述第一和所述第二存储单元的第一参考电路和第二参考电路，并具有分别提供第一参考电压和第二参考电压的相应输出端; 以及分压器，具有分别连接到第一参考电路和第二参考电路的输出端的第一连接节点和第二连接节点，以分别接收第一参考电压和第二参考电压，以及多个 中间节点以相等的距离提供相应的第三参考电压。

公开(公告)号：US20020149965A1

公开(公告)日：2002-10-17

申请号：US10076023

申请日：2002-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Rino Micheloni

IPC: G11C016/26

CPC classification number: G11C11/56 ,  G11C7/06 ,  G11C11/5621 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26

Abstract: The method for reading a memory cell includes supplying the cell with a first charge quantity through a capacitive integration element and reintegrating the first charge quantity through a plurality of second charge quantities supplied alternately and in succession to the capacitive integration element. In a first embodiment, the second charge quantities are initially stored in a plurality of capacitive charge-regeneration elements connected alternately and in succession to the capacitive integration element; the second charge quantities are then shared between the capacitive integration element and the capacitive charge-regeneration elements.

Abstract translation: 用于读取存储器单元的方法包括通过电容积分元件向单元提供第一电荷量，并通过交替地并依次提供给电容积分元件的多个第二电荷量重新整合第一电荷量。 在第一实施例中，第二电荷量最初被存储在多个电容性电荷再生元件中，这些元件是电容积分元件交替连续地连接的; 然后在电容积分元件和电容充电再生元件之间共享第二电荷量。

公开(公告)号：US20020149964A1

公开(公告)日：2002-10-17

申请号：US10047918

申请日：2002-01-14

Applicant: STMicroelectronics S.r.l.

Inventor： Giovanni Campardo ,  Rino Micheloni

IPC: G11C011/34

CPC classification number: G11C11/5621 ,  G11C7/067 ,  G11C11/56 ,  G11C11/5642 ,  G11C11/565 ,  G11C16/26

Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell by a capacitive element. The capacitive element is initially charged and then discharged linearly in a preset time, while the memory cell is biased at a constant voltage. In a first operating mode, initially a first capacitor and a second capacitor are respectively charged to a first charge value and to a second charge value. The second capacitor is discharged through the memory cell at a constant current in a preset time; the first charge is shared between the first capacitor and the second capacitor; and then the shared charge is measured.

Abstract translation: 用于读取存储器单元的方法是基于通过电容元件提供给存储单元的电流的时间积分。 电容元件最初被充电，然后在预设时间内线性地放电，同时存储单元被偏置在恒定电压。 在第一操作模式中，最初将第一电容器和第二电容器分别充电到第一充电值和第二充电值。 第二电容器在预定时间内以恒定电流通过存储单元放电; 第一电荷在第一电容器和第二电容器之间共享; 然后测量共享费用。

公开(公告)号：US20020097627A1

公开(公告)日：2002-07-25

申请号：US09960851

申请日：2001-09-21

Applicant: STMicroelectronics S.r.l.

Inventor： Andrea Sacco ,  Osama Khouri ,  Rino Micheloni ,  Guido Torelli

IPC: G11C005/00

CPC classification number: G11C16/08 ,  G11C5/147 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14

Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

Abstract translation: 这里描述的是一种非易失性存储器，包括根据全局字线和本地字线组织的存储器阵列; 全球排解码器; 一个本地行解码器; 用于提供全球行解码器的第一供应级; 以及用于提供本地行解码器的第二供应级; 以及用于偏置存储器阵列的存储单元的漏极和源极端子的第三供电级。 每个供电级包括由多个串联电阻器形成的相应电阻分压器，以及各自并联连接到相应电阻器的多个通栅CMOS开关。 非易失性存储器还包括用于控制供电级的通过栅极CMOS开关的控制电路和用于在存储器的读取和编程期间将控制电路的电源输入选择性地连接到第二电源级的输出的开关电路 并且在擦除存储器期间到达第三电源级的输出。

公开(公告)号：US20020181277A1

公开(公告)日：2002-12-05

申请号：US10123874

申请日：2002-04-16

Applicant: STMicroelectronics S.r.l.

Inventor： Rino Micheloni ,  Giovanni Campardo

IPC: G11C011/34

CPC classification number: G11C7/062 ,  G11C7/04 ,  G11C7/22 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/32 ,  G11C2207/063 ,  G11C2211/5634

Abstract: The method for timing reading of a memory cell envisages supplying the memory cell (with a constant current by means of a first capacitive element, integrating said current in a time interval, and controlling the duration of the time interval in such a way as to compensate for any deviations in the current from a nominal value. In particular, a reference current is supplied to a reference cell by means of a second capacitive element; next, a first voltage present on the second capacitive element is measured; finally, the memory cell is deactivated when the first voltage is equal to a second voltage, which is constant.

Abstract translation: 用于定时读取存储器单元的方法设想为存储器单元提供（通过第一电容元件的恒定电流，在时间间隔内积分所述电流，并以这样的方式来控制时间间隔的持续时间，以便补偿 特别是通过第二电容元件将参考电流提供给参考电池;接下来，测量存在于第二电容元件上的第一电压;最后，存储单元 当第一电压等于第二电压时，其被停用，该第二电压是恒定的。