公开(公告)号：US20160172231A1

公开(公告)日：2016-06-16

申请号：US14567567

申请日：2014-12-11

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Joe Lee ,  Yann Mignot ,  Brown C. Peethala

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/76802 ,  H01L21/76843

Abstract: A selective wet etching process is used, prior to air gap opening formation, to remove a sacrificial nitride layer from over a first region of an interconnect dielectric material containing a plurality of first conductive metal structures utilizing a titanium nitride hard mask portion located over a second region of the interconnect dielectric material as an etch mask. The titanium nitride hard mask portion located over the second region of the interconnect dielectric material is thereafter removed, again prior to air gap opening formation, utilizing another wet etch process. The wet etching processes are used instead of reactive ion etching.

Abstract translation: 在气隙开口形成之前，使用选择性湿蚀刻工艺，以从包含多个第一导电金属结构的互连电介质材料的第一区域上方除去牺牲氮化物层，所述第一导电金属结构利用位于第二层上的氮化钛硬掩模部分 互连电介质材料的区域作为蚀刻掩模。 此后，在气隙开口形成之前，再次移除位于互连电介质材料的第二区域之上的氮化钛硬掩模部分，利用另一湿蚀刻工艺。 使用湿蚀刻工艺代替反应离子蚀刻。

公开(公告)号：US20150076707A1

公开(公告)日：2015-03-19

申请号：US14030092

申请日：2013-09-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  Tokyo Electron Limited

Inventor： Yann Mignot ,  Yannick Feurprier ,  Wayne Meher

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76816 ,  H01L21/31144 ,  H01L21/76811 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for creating one or more vias in an integrated circuit structure and the integrated circuit structure. The method includes depositing a coating layer over a hard mask layer on the integrated circuit structure; locating an initial via pattern layer over the coating layer; and etching the pattern of the one or more initial openings in the coating layer and through openings in the hard mask layer. The coating layer is a conformal deposition of an oxide, a boron nitride, or other nitride. The initial via pattern layer has one or more initial openings located therein.

Abstract translation: 一种用于在集成电路结构和集成电路结构中创建一个或多个通孔的方法。 该方法包括在集成电路结构上的硬掩模层上沉积涂层; 将初始通孔图案层定位在涂层上; 并且蚀刻涂层中的一个或多个初始开口的图案并且通过硬掩模层中的开口。 涂层是氧化物，氮化硼或其它氮化物的共形沉积。 初始通孔图案层具有位于其中的一个或多个初始开口。

公开(公告)号：US10546743B2

公开(公告)日：2020-01-28

申请号：US15874654

申请日：2018-01-18

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Yann Mignot ,  Lawrence A. Clevenger ,  Carl Radens ,  Richard Stephen Wise ,  Yiheng Xu ,  Yannick Loquet ,  Hsueh-Chung Chen

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768

Abstract: Ultra-low-k dielectric materials used as inter-layer dielectrics in high-performance integrated circuits are prone to be structurally unstable. The Young's modulus of such materials is decreased, resulting in porosity, poor film strength, cracking, and voids. An alternative dual damascene interconnect process incorporates air gaps into a high modulus dielectric material to maintain structural stability while reducing capacitance between adjacent nanowires. Incorporation of an air gap having k=1.0 compensates for the use of a higher modulus film having a dielectric constant greater than the typical ultra-low-k (ULK) dielectric value of about 2.2. The higher modulus film containing the air gap is used as an insulator between adjacent metal lines, while a ULK film is retained to insulate vias. The dielectric layer between two adjacent metal lines thus forms a ULK/high-modulus dielectric bi-layer.

公开(公告)号：US10354927B2

公开(公告)日：2019-07-16

申请号：US16027707

申请日：2018-07-05

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20180144991A1

公开(公告)日：2018-05-24

申请号：US15874813

申请日：2018-01-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US09679899B2

公开(公告)日：2017-06-13

申请号：US14833857

申请日：2015-08-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US09385078B1

公开(公告)日：2016-07-05

申请号：US15064688

申请日：2016-03-09

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

公开(公告)号：US09768113B2

公开(公告)日：2017-09-19

申请号：US15152981

申请日：2016-05-12

Applicant: International Business Machines Corporation ,  Tokyo Electron Limited ,  STMicroelectronics, Inc.

Inventor： Yannick Feurprier ,  Joe Lee ,  Lars W. Liebmann ,  Yann Mignot ,  Terry A. Spooner ,  Douglas M. Trickett ,  Mehmet Yilmaz

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/033 ,  H01L21/311 ,  H01L21/321

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

公开(公告)号：US20170062426A1

公开(公告)日：2017-03-02

申请号：US14833857

申请日：2015-08-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract translation: 公开了集成电路，其中相邻pFET和nFET的应变特性可独立调节。 pFET在硅衬底上包括压应变SiGe，而nFET在应变弛豫SiGe衬底上包括拉伸应变硅。 相邻的n型和p型FinFET由通过镶嵌工艺形成的电绝缘区域分开。 在形成绝缘区域的过程中，允许支持n型器件的SiGe衬底弹性弛豫，从而限制SiGe衬底的晶格中的缺陷形成。

公开(公告)号：US09576852B2

公开(公告)日：2017-02-21

申请号：US14751380

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES, INC. ,  STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Ming He ,  Seowoo Nam ,  Yann Mignot ,  Jim Kelly ,  Raghuveer Patlotta ,  Theodorus Standaert

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/0217 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/528

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect in a first interlayer dielectric. A first cap is formed overlying the first interlayer dielectric adjacent to the interconnect, and a second interlayer dielectric is formed overlying the first interlayer dielectric, the interconnect, and the cap. A contact is formed through the second interlayer dielectric, where the contact includes an overlap region and a connection region. The overlap region directly overlies the first interlayer dielectric adjacent to the interconnect, and the connection region directly contacts the interconnect. The first cap is positioned between the overlap region and the first interlayer dielectric.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在第一层间电介质中形成互连。 第一盖形成在与互连件相邻的第一层间电介质上，并且形成覆盖第一层间电介质，互连和盖的第二层间电介质。 通过第二层间电介质形成触点，其中触点包括重叠区域和连接区域。 重叠区域直接覆盖与互连件相邻的第一层间电介质，并且连接区域直接接触互连。 第一盖位于重叠区域和第一层间电介质之间。