公开(公告)号：US11562927B2

公开(公告)日：2023-01-24

申请号：US17228164

申请日：2021-04-12

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Jean-Pierre Carrere ,  Jean-Luc Huguenin ,  Clement Pribat ,  Sarah Kuster

IPC: H01L21/768 ,  H01L21/82 ,  H01L21/84 ,  H01L21/762 ,  H01L21/74 ,  H01L21/02 ,  H01L29/06 ,  H01L27/12 ,  H01L21/8234

Abstract: A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

公开(公告)号：US11075177B2

公开(公告)日：2021-07-27

申请号：US16278313

申请日：2019-02-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre

IPC: H01L23/60 ,  H01L23/66 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

公开(公告)号：US20150300809A1

公开(公告)日：2015-10-22

申请号：US14442081

申请日：2013-09-19

Applicant: SOITEC ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Oleg Kononchuk ,  Didier Dutartre

IPC: G01B11/06 ,  G02B21/36 ,  H01L21/66

CPC classification number: G01B11/06 ,  G01B11/0633 ,  G01B11/30 ,  G02B21/361 ,  H01L22/12

Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to the given thickness difference, the thicknesses of the other layers being for their part identical in the two multilayer structures. The invention also relates to a measuring system implementing the method.

Abstract translation: 本发明涉及一种用于测量多层半导体结构的层中的厚度变化的方法，其特征在于，其包括：经由图像采集系统获取所述结构的表面的至少一个图像，所述图像通过反射 来自结构表面的几乎单色的光通量; 并且处理所述至少一个获取的图像，以便根据从表面反射的光的强度的变化来确定被测量层的厚度的变化，并且选择几乎单色光束的波长 对应于除了必须测量其厚度变化的层之外的结构层的反射率的最小灵敏度，层的反射率的灵敏度等于：反射率之间的差异 的两层多层结构，其中所述层具有给定的厚度差; 对于给定的厚度差，其他层的厚度在两个多层结构中的部分相同。 本发明还涉及实现该方法的测量系统。

公开(公告)号：US11978710B2

公开(公告)日：2024-05-07

申请号：US17359872

申请日：2021-06-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre

IPC: H01L23/00 ,  H01L21/762 ,  H01L23/66 ,  H01L29/06

CPC classification number: H01L23/66 ,  H01L21/76286 ,  H01L29/0646 ,  H01L29/0649 ,  H01L2223/6688

Abstract: An integrated circuit includes a substrate having at least one first domain and at least one second domain that is different from the at least one first domain. A trap-rich region is provided in the substrate at the locations of the at least one second domain only. Locations of the at least one first domain do not include the trap-rich region.

公开(公告)号：US20230361151A1

公开(公告)日：2023-11-09

申请号：US18298781

申请日：2023-04-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Jonathan Fantuz ,  Alain Inard ,  Didier Dutartre

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14627

Abstract: In accordance with an embodiment, a method for manufacturing an optical device on a support substrate includes: forming first microlens structures on the support substrate using a first photolithography process such that the first microlens structures are separated from one another; deforming the first microlens structures so as to give the first microlens structures a curved shape, wherein the first microlens structures are separated from one another by spacer regions after deformation; forming second microlens structures substrate using a second photolithography process such that the second microlens structures extend over the first microlens structures; and deforming the second microlens structures such that the second microlens structures have a curved form matching the curved shape of the first microlens structures and extend partly into the spacer regions between the first microlens structures.

公开(公告)号：US11757054B2

公开(公告)日：2023-09-12

申请号：US17324619

申请日：2021-05-19

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre

IPC: H01L31/028 ,  G01S7/4865 ,  H01L27/146 ,  H01L31/103

CPC classification number: H01L31/028 ,  G01S7/4865 ,  H01L27/14649 ,  H01L31/1037

Abstract: An integrated optical sensor is formed by a pinned photodiode. A semiconductor substrate includes a first semiconductor region having a first type of conductivity located between a second semiconductor region having a second type of conductivity opposite to the first type one and a third semiconductor region having the second type of conductivity. The third semiconductor region is thicker, less doped and located deeper in the substrate than the second semiconductor region. The third semiconductor region includes both silicon and germanium. In one implementation, the germanium within the third semiconductor region has at least one concentration gradient. In another implementation, the germanium concentration within the third semiconductor region is substantially constant.

公开(公告)号：US20130095636A1

公开(公告)日：2013-04-18

申请号：US13653911

申请日：2012-10-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Zahra Aitfqirali-Guerry ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC: H01L21/762

CPC classification number: H01L21/76237

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract translation: 在包括硅并且具有前侧的半导体衬底中产生至少一个深沟槽隔离的方法可以包括从前侧形成半导体衬底中的至少一个空腔。 该方法可以包括在腔的壁上共形沉积掺杂剂原子，并且在空腔的壁附近形成掺杂有掺杂剂原子的硅区。 该方法还可以包括用填充材料填充空腔以形成至少一个深沟槽隔离。

公开(公告)号：US09759546B2

公开(公告)日：2017-09-12

申请号：US14442081

申请日：2013-09-19

Applicant: SOITEC ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Oleg Kononchuk ,  Didier Dutartre

IPC: G01B11/28 ,  G01B11/06 ,  G01B11/30 ,  H01L21/66 ,  G02B21/36

CPC classification number: G01B11/06 ,  G01B11/0633 ,  G01B11/30 ,  G02B21/361 ,  H01L22/12

Abstract: The invention relates to a method for measuring thickness variations in a layer of a multilayer semiconductor structure, characterized in that it comprises: acquiring, via an image acquisition system, at least one image of the surface of the structure, the image being obtained by reflecting an almost monochromatic light flux from the surface of the structure; and processing the at least one acquired image in order to determine, from variations in the intensity of the light reflected from the surface, variations in the thickness of the layer to be measured, and in that the wavelength of the almost monochromatic light flux is chosen to correspond to a minimum of the sensitivity of the reflectivity of a layer of the structure other than the layer the thickness variations of which must be measured, the sensitivity of the reflectivity of a layer being equal to the ratio of: the difference between the reflectivities of two multilayer structures for which the layer in question has a given thickness difference; to the given thickness difference, the thicknesses of the other layers being for their part identical in the two multilayer structures. The invention also relates to a measuring system implementing the method.

公开(公告)号：US08975154B2

公开(公告)日：2015-03-10

申请号：US13653911

申请日：2012-10-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Zahra Aitfqirali-Guerry ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76237

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract translation: 在包括硅并且具有前侧的半导体衬底中产生至少一个深沟槽隔离的方法可以包括从前侧形成半导体衬底中的至少一个空腔。 该方法可以包括在腔的壁上共形沉积掺杂剂原子，并且在空腔的壁附近形成掺杂有掺杂剂原子的硅区。 该方法还可以包括用填充材料填充空腔以形成至少一个深沟槽隔离。

公开(公告)号：US12211754B2

公开(公告)日：2025-01-28

申请号：US17729191

申请日：2022-04-26

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Pierpaolo Monge Roffarello ,  Isabella Mica ,  Didier Dutartre ,  Alexandra Abbadie

IPC: H01L21/8249 ,  H01L21/02 ,  H01L21/324 ,  H01L21/763 ,  H01L27/06

Abstract: A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.