公开(公告)号：US10115666B2

公开(公告)日：2018-10-30

申请号：US14221401

申请日：2014-03-21

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Guilhem Bouton ,  Patrick Regnier

IPC: H01L21/4763 ,  H01L23/528 ,  H01L21/033 ,  H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  G03F1/50 ,  H01L23/00 ,  G03F1/38

Abstract: A method for making a photolithography mask for formation of electrically conducting contact pads between tracks of a metallization level and electrically active zones of integrated circuits formed on a semiconductor wafer includes forming a first mask region including first opening zones intended for the formation of the contact pads. The first opening zone has a first degree of opening that is below a threshold. A second mask region including additional opening zones is formed, with the overall degree of opening of the mask being greater than or equal to the threshold.

公开(公告)号：US20180145027A1

公开(公告)日：2018-05-24

申请号：US15596877

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76804 ,  H01L21/76831 ,  H01L21/7685 ,  H01L21/76883 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/573

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer and an inter-metallization level insulating layer. An electrical discontinuity is provided between a via of the via level and a metal track of the lower metallization level. The electrical discontinuity is formed by an additional insulating layer having a material composition identical to that of the inter-metallization level insulating layer. The electrical discontinuity is situated between a bottom of the via and a top of the metal track, with the discontinuity being bordered by the insulating encapsulation layer.

公开(公告)号：US20150255540A1

公开(公告)日：2015-09-10

申请号：US14715090

申请日：2015-05-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/06 ,  H01L29/78 ,  H01L23/522

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66568 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region.

Abstract translation: 集成电路包括衬底和至少一个NMOS晶体管，其在衬底中具有由沟槽绝缘区域包围的有源区域。 晶体管，有源区和沟槽绝缘区被额外的绝缘区覆盖。 金属接触件延伸穿过附加绝缘区域以与沟槽绝缘区域接触。 金属接触可能渗入沟槽绝缘区域。

公开(公告)号：US20150249132A1

公开(公告)日：2015-09-03

申请号：US14627281

申请日：2015-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L29/06

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

Abstract translation: 集成电路包括衬底和至少一个对压缩应力非常敏感的部件，其至少部分地布置在由绝缘区域限制的衬底的有源区域内。 为了解决有源区域中的压缩应力，电路还包括位于至少绝缘区域中的至少一个电惰性沟槽，并且包含被配置为减小有源区域中的压缩应力的内部区域。 内部填充多晶硅。 多晶硅填充沟槽可以进一步延伸穿过绝缘区域并进入衬底。

公开(公告)号：US10770547B2

公开(公告)日：2020-09-08

申请号：US16657409

申请日：2019-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L29/06 ,  H01L29/78 ,  H01L27/112 ,  H01L21/762 ,  H01L21/763

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20180145039A1

公开(公告)日：2018-05-24

申请号：US15596772

申请日：2017-05-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Guilhem Bouton ,  Mathieu Lisart

IPC: H01L23/00 ,  H01L23/28 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/56

CPC classification number: H01L23/57 ,  H01L21/56 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/28 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/573

Abstract: An integrated circuit includes an interconnection part with a via level situated between a lower metallization level and an upper metallization level. The lower metallization level is covered by an insulating encapsulation layer. An electrical discontinuity between a first via of the via level and a first metal track of the lower metallization level is provided at the level of the insulating encapsulation layer. The electrical discontinuity is formed prior to formation of any via of the via level and prior to any metal track of the upper metallization level. The electrical discontinuity may comprise: a portion of an additional insulating layer extending over the insulating encapsulation layer; a portion of the insulating encapsulation layer; or an insulating oxide on a top surface of the first metal track.

公开(公告)号：US20170194267A1

公开(公告)日：2017-07-06

申请号：US15466396

申请日：2017-03-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L27/02 ,  H01L21/768

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

公开(公告)号：US20160093696A1

公开(公告)日：2016-03-31

申请号：US14953692

申请日：2015-11-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem Bouton ,  Pascal Fornara ,  Christian Rivero

IPC: H01L29/10 ,  H01L21/763 ,  H01L27/112 ,  H01L21/762

CPC classification number: H01L29/1083 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/11293 ,  H01L29/0649 ,  H01L29/78 ,  H01L29/7846

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20160064339A1

公开(公告)日：2016-03-03

申请号：US14829292

申请日：2015-08-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Guilhem Bouton

IPC: H01L23/00 ,  H01L21/768

CPC classification number: H01L23/576 ,  G06F17/5068 ,  H01L21/768 ,  H01L21/76838 ,  H01L23/573 ,  H01L27/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate with several functional blocks formed thereon. At least two identical functional blocks are respectively disposed at two or more different locations on the integrated circuit. Electrically inactive dummy modules in the neighborhoods and/or inside of the functional blocks are provided, wherein at least two different electrically inactive dummy modules are includes in the respective neighborhoods and/or inside of the at least two identical functional blocks.

Abstract translation: 集成电路包括其上形成有多个功能块的基板。 至少两个相同的功能块分别设置在集成电路上的两个或更多个不同位置处。 提供了在功能块的附近和/或内部的电活动的虚拟模块，其中至少两个不同的电不活动的虚拟模块包括在相应的邻域和/或至少两个相同功能块的内部。

公开(公告)号：US09263518B2

公开(公告)日：2016-02-16

申请号：US14300663

申请日：2014-06-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L23/522

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66568 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.

Abstract translation: 集成电路包括衬底和至少一个NMOS晶体管，其在衬底中具有由绝缘区域包围的有源区域。 绝缘区域形成为包括至少一个区域，其中绝缘区域具有通过由基板的一部分形成的分离区域彼此分离的两个绝缘区域。