公开(公告)号：US20250015016A1

公开(公告)日：2025-01-09

申请号：US18887429

申请日：2024-09-17

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00 ,  G06F21/75 ,  G06F21/79 ,  G06F21/87 ,  H01L23/522 ,  H01L29/788 ,  H10B41/35

Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.

公开(公告)号：US20210335994A1

公开(公告)日：2021-10-28

申请号：US17370397

申请日：2021-07-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: H01L29/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

公开(公告)号：US20210217711A1

公开(公告)日：2021-07-15

申请号：US17217005

申请日：2021-03-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: H01L23/62 ,  H01H85/02 ,  H01L23/525 ,  H01L21/66

Abstract: A semiconductor wafer includes first zones containing integrated circuits, each first zone including a substrate and a sealing ring at a periphery of the substrate. The first zones are separated from each other by second zones defining cutting lines or paths. The integrated circuit includes an electrically conductive fuse that extends between a first location inside the integrated circuit and a second location situated outside the integrated circuit beyond one of the cutting lines. This electrically conductive fuse includes a portion that passes through the sealing ring and another portion that straddles the adjacent cutting line. The portion of the fuse that passes through is electrically isolated from the sealing ring and from the substrate. The straddling portion is configured to be sliced, when cutting the wafer along the cutting line, so as to cause the fuse to change from an electrical on state to an electrical off state.

公开(公告)号：US20210018458A1

公开(公告)日：2021-01-21

申请号：US16928551

申请日：2020-07-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Matthias VIDAL-DHO ,  Quentin HUBERT ,  Pascal FORNARA

IPC: G01N27/22 ,  H01L23/00 ,  G01N27/12

Abstract: Moisture that is possibly present in an integrated circuit is detected autonomously by the integrated circuit itself. An interconnect region of the integrated circuit includes a metal level with a first track and a second track which are separated by a dielectric material. A detection circuit applies a potential difference between the first and second tracks. A current circulating in one of the first and second tracks in response to the potential difference is measured and compared to a threshold. If the current exceeds the threshold, this is indicative of the presence of moisture which renders said dielectric material less insulating.

公开(公告)号：US20200075506A1

公开(公告)日：2020-03-05

申请号：US16549000

申请日：2019-08-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI ,  Pascal FORNARA

IPC: H01L23/00 ,  H01L27/01 ,  H01L21/70 ,  G04F1/00

Abstract: An ultralong time constant time measurement device includes elementary capacitive elements that are connected in series. Each elementary capacitive element is formed by a stack of a first conductive region, a dielectric layer having a thickness suited for allowing charge to flow by direct tunneling effect, and a second conductive region. The first conductive region is housed in a trench extending from a front face of a semiconductor substrate down into the semiconductor substrate. The dielectric layer rests on the first face of the semiconductor substrate and in particular on a portion of the first conductive region in the trench. The second conductive region rests on the dielectric layer.

公开(公告)号：US20190165105A1

公开(公告)日：2019-05-30

申请号：US16241762

申请日：2019-01-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem BOUTON ,  Pascal FORNARA ,  Christian RIVERO

IPC: H01L29/10 ,  H01L27/112 ,  H01L29/78 ,  H01L21/763 ,  H01L21/762 ,  H01L29/06

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20190113897A1

公开(公告)日：2019-04-18

申请号：US16155355

申请日：2018-10-09

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA

IPC: G05B19/042 ,  H02J7/00

Abstract: A system, supplied by a power supply, is switched into standby mode by an electronic device that includes a charging input coupled to a charge voltage obtained from the voltage delivered by the power supply. A first input is coupled to the power supply and a power supply output is coupled to the system. A storage capacitive element is coupled to the charging input and configured to be charged by the charge voltage. A switching circuit, coupled between the first input and the power supply output, disconnects the power supply output from the first input when the voltage across the terminals of the storage capacitive element is higher than a threshold. A discharge circuit discharges the storage capacitive element so that the capacitor voltage becomes lower than the threshold. The switching circuit further re-connects the first input to the power supply output at the end of the discharge period.

公开(公告)号：US20220139899A1

公开(公告)日：2022-05-05

申请号：US17516920

申请日：2021-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Roberto SIMOLA

IPC: H01L27/01 ,  H01L27/11531 ,  H01L27/11529 ,  H01L21/70

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US20200052073A1

公开(公告)日：2020-02-13

申请号：US16657409

申请日：2019-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Guilhem BOUTON ,  Pascal FORNARA ,  Christian RIVERO

IPC: H01L29/10 ,  H01L29/06 ,  H01L21/762 ,  H01L21/763 ,  H01L29/78 ,  H01L27/112

Abstract: An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.

公开(公告)号：US20200035623A1

公开(公告)日：2020-01-30

申请号：US16518755

申请日：2019-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Fabrice MARINET

IPC: H01L23/00

Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.