公开(公告)号：US20240276894A1

公开(公告)日：2024-08-15

申请号：US18646334

申请日：2024-04-25

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Roberto SIMOLA ,  Yohann MOUSTAPHA-RABAULT

IPC: H10N70/20 ,  H10B63/00 ,  H10N70/00

CPC classification number: H10N70/231 ,  H10B63/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/066 ,  H10N70/068 ,  H10N70/882 ,  H10N70/883

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

公开(公告)号：US20240312977A1

公开(公告)日：2024-09-19

申请号：US18668639

申请日：2024-05-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Roberto SIMOLA

IPC: H01L27/01 ,  H01L21/70 ,  H10B41/41 ,  H10B41/42

CPC classification number: H01L27/016 ,  H01L21/707 ,  H10B41/41 ,  H10B41/42

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US20200265894A1

公开(公告)日：2020-08-20

申请号：US16866955

申请日：2020-05-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Roberto SIMOLA

IPC: G11C16/04 ,  H01L29/423 ,  H01L27/11517

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US20220367497A1

公开(公告)日：2022-11-17

申请号：US17734963

申请日：2022-05-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Roberto SIMOLA ,  Philippe BOIVIN

IPC: H01L27/11529 ,  H01L27/11524

Abstract: The integrated circuit of a non-volatile memory of the electrically erasable and programmable type includes memory cells, each memory cell having a state transistor including a gate structure comprising a control gate and a floating gate disposed on a face of a semiconductor well, as well as a source region and a drain region in the semiconductor well. The drain region includes a first capacitive implant region positioned predominantly under the gate structure and a lightly doped region positioned predominantly outside the gate structure. The source region includes a second capacitive implant region positioned predominantly outside the gate structure, the source region not including a lightly doped region.

公开(公告)号：US20220140232A1

公开(公告)日：2022-05-05

申请号：US17507645

申请日：2021-10-21

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe BOIVIN ,  Roberto SIMOLA ,  Yohann MOUSTAPHA-RABAULT

IPC: H01L45/00 ,  H01L27/24

Abstract: The present description concerns a device including phase-change memory cells, each memory cell including a first resistive element in lateral contact with a second element made of a phase-change material.

公开(公告)号：US20200035304A1

公开(公告)日：2020-01-30

申请号：US16048524

申请日：2018-07-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Roberto SIMOLA

IPC: G11C16/04 ,  H01L29/423 ,  H01L27/11517

Abstract: An EEPROM includes a floating gate transistor having a source region, a channel region and a drain region. A first capa implant zone on a drain-side of the floating gate transistor has a first dopant concentration level. A second capa implant zone in the first capa implant zone adjacent the drain region has a second dopant concentration level that is greater than the first dopant concentration level. A gate oxide region insulates the floating gate electrode from the channel region, first capa implant zone and second capa implant zone. A thickness of the gate oxide region is thinner at the second capa implant zone than at the channel region and first capa implant zone.

公开(公告)号：US20230299127A1

公开(公告)日：2023-09-21

申请号：US18180025

申请日：2023-03-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francois TAILLIET ,  Loic WELTER ,  Maria-Paz DUMITRESCU ,  Roberto SIMOLA

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L21/28 ,  H01L29/788 ,  H01L21/762 ,  H10B41/10 ,  H10B41/35

CPC classification number: H01L29/0607 ,  H01L29/7835 ,  H01L27/0922 ,  H01L29/6659 ,  H01L29/402 ,  H01L29/42324 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883 ,  H01L21/76224 ,  H10B41/10 ,  H10B41/35

Abstract: The integrated circuit comprises at least one transistor including a separate gate structure and field plate, disposed on a front face of a semiconductor substrate, and a doped conduction region in the semiconductor substrate located plumb with an edge of the gate structure and plumb with an edge of the field plate.

公开(公告)号：US20220139899A1

公开(公告)日：2022-05-05

申请号：US17516920

申请日：2021-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal FORNARA ,  Roberto SIMOLA

IPC: H01L27/01 ,  H01L27/11531 ,  H01L27/11529 ,  H01L21/70

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US20220123119A1

公开(公告)日：2022-04-21

申请号：US17504198

申请日：2021-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian RIVERO ,  Philippe BOIVIN ,  Francois TAILLIET ,  Roberto SIMOLA

IPC: H01L29/423 ,  H01L27/11524 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A memory transistor for a non-volatile memory cell includes a source region and a drain region implanted in a semiconductor substrate. The source region is spaced from the drain region. A double gate region for the memory transistor extends at least partly in depth in the semiconductor substrate between the source region and the drain region and further extends beyond this source region and this drain region. The memory cell further includes a selection transistor having a gate region that partially extends over the double gate region for the memory transistor.

公开(公告)号：US20170148926A1

公开(公告)日：2017-05-25

申请号：US15402758

申请日：2017-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Roberto SIMOLA ,  Pascal FORNARA

IPC: H01L29/866 ,  H01L29/66 ,  H01L29/739 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/866 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/402 ,  H01L29/407 ,  H01L29/66106 ,  H01L29/7391

Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.