公开(公告)号：US20250069652A1

公开(公告)日：2025-02-27

申请号：US18942973

申请日：2024-11-11

Applicant: STMicroelectronics International N.V.

Inventor： Kedar Janardan DHORI

IPC: G11C11/417 ,  G11C11/412

Abstract: Disclosed herein is a method of operating a static random access memory (SRAM) device in retention mode. The method includes powering an array of SRAM cells between first and second voltages in retention mode, detecting process variation information about the array of SRAM cells, and generating a control word based thereupon. The method continues with generating a reference voltage that is proportional to absolute temperature and having a magnitude curve that is set by the control word, and then maintaining the second voltage as being equal to the reference voltage.

公开(公告)号：US20240395319A1

公开(公告)日：2024-11-28

申请号：US18791901

申请日：2024-08-01

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/418

Abstract: SRAM cells are connected in columns by bit lines and connected in rows by first and second word lines coupled to first and second data storage sides of the SRAM cells. First the first word lines are actuated in parallel and then next the second word lines are actuated in parallel in first and second phases, respectively, of an in-memory compute operation. Bit line voltages in the first and second phases are processed to generate an in-memory compute operation decision. A low supply node reference voltage for the SRAM cells is selectively modulated between a ground voltage and a negative voltage. The first data storage side receives the negative voltage and the second data storage side receives the ground voltage during the second phase. Conversely, the second data storage side receives the negative voltage and the first data storage side receives the ground voltage during the first phase.

公开(公告)号：US20240363187A1

公开(公告)日：2024-10-31

申请号：US18635569

申请日：2024-04-15

Applicant: STMicroelectronics International N.V.

Inventor： Praveen Kumar VERMA ,  Christophe LECOCQ ,  Yagnesh Dineshbhai VADERIYA ,  Anuj DHILLON ,  Cedric ESCALLIER ,  Harsh RAWAT ,  Kedar Janardan DHORI

IPC: G11C29/46 ,  G11C29/02 ,  G11C29/32

CPC classification number: G11C29/46 ,  G11C29/022 ,  G11C29/32 ,  G11C2029/3202

Abstract: A memory system disclosed herein features left and/or right memory banks, with left and/or right input/output (IO) blocks aligned with the memory banks for managing data input and output. A control section, situated between the left and right input/output blocks, oversees memory operations, receives control signals, and performs stuck-at testing. The control section includes fault detection logic designed to output a first logic value (e.g., logic low) if logic values at each of its external inputs are identical, but output a second logic value (e.g., logic high) if not. The fault detection logic is capable of detecting stuck-at faults in the external inputs by performing both stuck-at-0 and stuck-at-1 testing. If only stuck-at-0 or stuck-at-1 faults are detected, the fault detection logic can pinpoint those faults by iteratively changing input values at each of its external inputs and observing the output of the fault detection logic.

公开(公告)号：US20230410862A1

公开(公告)日：2023-12-21

申请号：US18136491

申请日：2023-04-19

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Kedar Janardan DHORI ,  Promod KUMAR ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C7/16 ,  G11C7/12 ,  G11C8/08

CPC classification number: G11C7/16 ,  G11C8/08 ,  G11C7/12

Abstract: An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by local bit lines. A row controller circuit selectively actuates one word line per sub-array for an in-memory compute operation. A global bit line is capacitively coupled to many local bit lines in either a column direction or row direction. An analog global output voltage on each global bit line is an average of local bit line voltages on the capacitively coupled local bit lines. The analog global output voltage is sampled and converted by an analog-to-digital converter (ADC) circuit to generate a digital decision signal output for the in-memory compute operation.

公开(公告)号：US20230350483A1

公开(公告)日：2023-11-02

申请号：US18338950

申请日：2023-06-21

Applicant: STMICROELECTRONICS S.r.l. ,  STMicroelectronics International N.V.

Inventor： Nitin CHAWLA ,  Anuj GROVER ,  Giuseppe DESOLI ,  Kedar Janardan DHORI ,  Thomas BOESCH ,  Promod KUMAR

IPC: G05F3/24 ,  G11C11/413 ,  G06F1/3234 ,  G06F1/3287 ,  G06F15/78

CPC classification number: G06F1/3275 ,  G05F3/24 ,  G06F1/3287 ,  G06F15/7821 ,  G11C11/413

Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.

公开(公告)号：US20240177769A1

公开(公告)日：2024-05-30

申请号：US18522547

申请日：2023-11-29

Applicant: STMicroelectronics International N.V.

Inventor： Promod KUMAR ,  Kedar Janardan DHORI ,  Harsh RAWAT ,  Nitin CHAWLA ,  Manuj AYODHYAWASI

IPC: G11C11/419 ,  G11C5/14 ,  G11C8/08

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C8/08

Abstract: A memory array includes memory cells arranged in rows and columns where each row includes a word line connected to memory cells of the row and each column includes a bit line connected to memory cells of the column. Each memory cell stores a bit of weight data for an in-memory computation operation. A row controller circuit coupled to the word lines through drive circuits is configured to simultaneously actuate multiple word lines during the in-memory computation operation. A column processing circuit includes a discharge time sensing circuit for each column that generates an analog signal indicative of a time taken during the in-memory computation operation to discharge the bit line from a precharge voltage to a threshold voltage. The analog signals are converted to digital signal and a computation circuitry performs digital signal processing calculations on the digital signals to generate a decision output for the in-memory computation operation.

公开(公告)号：US20240112748A1

公开(公告)日：2024-04-04

申请号：US18228118

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Tanuj KUMAR ,  Hitesh CHAWLA ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G11C29/12015 ,  G11C29/32 ,  G11C2029/1204

Abstract: A memory circuit includes an address port, a data input port and a data output port. An upstream shadow logic circuit is coupled to provide address data to the address port of the memory circuit and input data to the data input port of the memory circuit. A downstream shadow logic circuit is coupled to receive output data from the data output port of the memory circuit. The memory circuit includes a bypass path between the address port and the data output port. This bypass path is activated during a testing operation to pass bits of the address data (forming test data) applied by upstream shadow logic circuit from the address port to the data output port.

公开(公告)号：US20240071546A1

公开(公告)日：2024-02-29

申请号：US18227545

申请日：2023-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Hitesh CHAWLA ,  Tanuj KUMAR ,  Bhupender SINGH ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G11C29/12 ,  G11C29/36

CPC classification number: G11C29/1201 ,  G11C29/36 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/3602

Abstract: The memory array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder circuit supports two modes of memory circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. Both BIST and ATPG testing of the input/output circuit are supported. For BIST testing, multiple data paths between the bit line inputs and the column data output are selectively controlled to provide complete circuit testing.

公开(公告)号：US20240071429A1

公开(公告)日：2024-02-29

申请号：US18233562

申请日：2023-08-14

Applicant: STMicroelectronics International N.V.

Inventor： Harsh RAWAT ,  Nitin CHAWLA ,  Promod KUMAR ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1009 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/12

Abstract: The memory array of a circuit includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A control circuit supports two modes of circuit operation: a first mode where only one word line in the memory array is actuated during a memory read and a second mode where one word line per sub-array are simultaneously actuated during the memory read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. In memory computation operations are performed in the second mode as a function of feature data and weight data stored in the memory.

公开(公告)号：US20240069096A1

公开(公告)日：2024-02-29

申请号：US18228048

申请日：2023-07-31

Applicant: STMicroelectronics International N.V.

Inventor： Bhupender SINGH ,  Hitesh CHAWLA ,  Tanuj KUMAR ,  Harsh RAWAT ,  Kedar Janardan DHORI ,  Manuj AYODHYAWASI ,  Nitin CHAWLA ,  Promod KUMAR

IPC: G01R31/317 ,  G11C11/418 ,  G11C11/419

CPC classification number: G01R31/31724 ,  G11C11/418 ,  G11C11/419

Abstract: An array of a memory includes sub-arrays with memory cells arranged in a row-column matrix where each row includes a word line and each sub-array column includes a local bit line. A row decoder supports two modes of memory operation: a first mode where only one word line in the memory array is actuated during a read and a second mode where one word line per sub-array are simultaneously actuated during the read. An input/output circuit for each column includes inputs to the local bit lines of the sub-arrays, a column data output coupled to the bit line inputs, and a sub-array data output coupled to each bit line input. BIST testing of the input/output circuit is supported through data at both the column data output and the sub-array data outputs in order to confirm proper memory operation in support of both the first and second modes of operation.