公开(公告)号：US20030038338A1

公开(公告)日：2003-02-27

申请号：US10179462

申请日：2002-06-25

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Norbert Colombet ,  Phillippe Candelier

IPC: H01L029/00

CPC classification number: H01L23/5258 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/525 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes multiple layers of integrated electronic components, and at least one electrical connection strip defining a fusible strip in one of the layers. An end of the fusible strip is connected to an integrated electronic component. An intermediate electrical connection and heat dissipation structure and a screen are disposed between the fusible strip and the integrated electronic component.

Abstract translation: 半导体器件包括多层集成电子元件，以及至少一个电连接条，其在层之一中限定可熔条。 可熔条的端部连接到集成电子部件。 中间电气连接和散热结构和屏幕设置在可熔条和集成电子部件之间。

公开(公告)号：US20020176289A1

公开(公告)日：2002-11-28

申请号：US10117446

申请日：2002-04-03

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Cyrille Dray ,  Daniel Caspar

IPC: G11C007/00

CPC classification number: G11C16/0416 ,  G11C16/0408

Abstract: A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

Abstract translation: FAMOS存储单元被电擦除。 可以通过向基板施加比施加到源极的电压的低至少4伏的电压和施加到漏极的电压来电存储FAMOS存储单元。 施加到基板的电压也小于预定的限制，高于该预定限度，存储单元被破坏。

公开(公告)号：US20020159308A1

公开(公告)日：2002-10-31

申请号：US10062271

申请日：2002-02-01

Applicant: STMicroelectronics S.A.

Inventor： Richard Fournel ,  Leila Sedjai Aitouarab

IPC: G11C007/00

CPC classification number: G11C16/3431 ,  G11C16/3418

Abstract: Reference cells are refreshed in a non-volatile memory that includes a plurality of memory cells. A selected reference cell and a non-used memory cell are read simultaneously, and a signal read from the reference cell is compared to a signal read from the non-used memory cell. A refresh signal for refreshing the reference cell is supplied when the signal read therefrom is less than the signal read from the non-used memory cell.

Abstract translation: 参考单元在包括多个存储单元的非易失性存储器中刷新。 同时读取选择的参考单元和未使用的存储单元，并将从参考单元读取的信号与从未使用的存储单元读取的信号进行比较。 当从其读取的信号小于从未使用的存储单元读取的信号时，提供刷新参考单元的刷新信号。

公开(公告)号：US20010050387A1

公开(公告)日：2001-12-13

申请号：US09814177

申请日：2001-03-21

Applicant: STMicroelectronics S.A.

Inventor： Thomas Skotnicki ,  Didier Dutartre ,  Pascal Ribot ,  Maryse Paoli ,  Richard Fournel

IPC: H01L029/76

CPC classification number: H01L29/66825 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42336

Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

Abstract translation: 非易失性存储器包括在源极和漏极区域之间的衬底中延伸的浮动栅极。 通道区域可以被两个绝缘层限制。 本发明特别适用于使用CMOS技术的EPROM，EEPROM，闪存和单电子存储器。