公开(公告)号：US10109329B2

公开(公告)日：2018-10-23

申请号：US15471028

申请日：2017-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

IPC: G11C7/06 ,  G11C7/22 ,  G11C7/10

Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

公开(公告)号：US09755632B2

公开(公告)日：2017-09-05

申请号：US14826017

申请日：2015-08-13

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Fabio De Santis

IPC: H03L5/00 ,  H03K17/10

CPC classification number: H03K17/102

Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.

公开(公告)号：US09691493B1

公开(公告)日：2017-06-27

申请号：US15244664

申请日：2016-08-23

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Design & Application S.R.O.

Inventor： Marco Pasotti ,  Fabio De Santis ,  Roberto Bregoli ,  Dario Livornesi ,  Sandor Petenyi

IPC: G11C16/10 ,  G11C16/30 ,  H01L27/11521 ,  G11C16/28 ,  G11C16/04 ,  G11C5/14

CPC classification number: G11C16/30 ,  G05F3/30 ,  G11C5/147 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/28 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/1156 ,  H03F3/45188 ,  H03F3/45475 ,  H03F2200/456 ,  H03F2203/45341 ,  H03F2203/45342 ,  H03F2203/45528 ,  H03F2203/45674 ,  H03F2203/45676

Abstract: A device for generating a reference voltage includes a first non-volatile memory cell provided with a control-gate transistor and a reading transistor. The control-gate transistor includes a gate terminal, a body, a first conduction terminal and a second conduction terminal. The first conduction terminal and the second conduction terminal are connected together to form a control-gate terminal. The reading transistor includes a gate terminal that is connected to the gate terminal of the control-gate transistor to form a floating-gate terminal, a body, a third conduction terminal and a fourth conduction terminal. The device also includes a second, equivalent, memory cell. The source terminal of the first non-volatile memory cell and the source terminal of the second equivalent memory cell are connected together.

公开(公告)号：US09159425B2

公开(公告)日：2015-10-13

申请号：US14089016

申请日：2013-11-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Ganesh Raj R ,  Fabio De Santis

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/0433

Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.

Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。

公开(公告)号：US20150146490A1

公开(公告)日：2015-05-28

申请号：US14089016

申请日：2013-11-25

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Vikas Rana ,  Ganesh Raj R ,  Fabio De Santis

IPC: G11C16/14

CPC classification number: G11C16/0433

Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.

Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。

公开(公告)号：US20230198386A1

公开(公告)日：2023-06-22

申请号：US18168936

申请日：2023-02-14

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US20220352817A1

公开(公告)日：2022-11-03

申请号：US17866372

申请日：2022-07-15

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Marco Pasotti ,  Fabio De Santis

IPC: H02M3/07

Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.

公开(公告)号：US10658364B2

公开(公告)日：2020-05-19

申请号：US15908575

申请日：2018-02-28

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Fabio De Santis ,  Vikas Rana

IPC: H01L27/105 ,  H01L27/11521 ,  G11C29/00 ,  H01L27/112 ,  H01L27/11519 ,  H01L27/11558 ,  G11C16/04 ,  H01L21/66

Abstract: According to principles as discussed herein, an EEPROM cell is provided and then, after testing the code, using the exact same architecture, transistors, memory cells, and layout, the EEPROM cell is converted to a read-only memory (“ROM”) cell. This conversion is done on the very same integrated circuit die using the same layout, design, and timing with only a single change in an upper level mask in the memory array. In one embodiment, the mask change is the via mask connecting metal 1 to poly. This allows the flexibility to store the programming code as non-volatile memory code, and then after it has been tested, at time selected by the customer, some or all of that code from a code that can be written to a read-only code that is stored in a ROM cell that is composed the same transistors and having the same layout.

公开(公告)号：US20170200483A1

公开(公告)日：2017-07-13

申请号：US15471028

申请日：2017-03-28

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

IPC: G11C7/22 ,  G11C7/06

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.

公开(公告)号：US09640230B2

公开(公告)日：2017-05-02

申请号：US14938304

申请日：2015-11-11

Applicant: STMicroelectronics S.r.l.

Inventor： Marcella Carissimi ,  Marco Pasotti ,  Fabio De Santis

IPC: G11C16/28 ,  G11C7/06 ,  G11C7/08 ,  G11C16/04

CPC classification number: G11C7/22 ,  G11C7/06 ,  G11C7/062 ,  G11C7/08 ,  G11C7/10 ,  G11C16/0441 ,  G11C16/28

Abstract: A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector of the non-volatile memory is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.