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公开(公告)号：US20170344310A1
公开(公告)日：2017-11-30
申请号：US15331470
申请日：2016-10-21
Inventor： Michael Peeters , Fabrice Marinet , Jean-Louis Modave , Fabrice Romain
CPC classification number: G06F3/0659 , G06F3/0611 , G06F3/064 , G06F3/0673 , G06F21/52 , G06F21/554 , G06F21/566 , G06F2221/034 , G09C1/00 , H04L9/004 , H04L2209/046 , H04L2209/12
Abstract: An algorithm execution method includes carrying out a first execution of the algorithm by a processing unit, sending at least one first result, which is to be written into a memory, to a memory management circuit, and storing said first result into a first area of the volatile memory. The method also includes carrying out a second execution of the algorithm by the processing unit, sending at least one second result, which is to be written into the memory, to the memory management circuit, and applying, by means of the memory management circuit, a different processing for the at least one second result in the second execution than was applied for the at least one first results in the first execution.
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公开(公告)号：US11715705B2
公开(公告)日：2023-08-01
申请号：US16932082
申请日：2020-07-17
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pascal Fornara , Fabrice Marinet
IPC: H01L29/788 , G06F21/75 , G06F21/79 , H01L23/522 , H10B41/35 , H01L23/00 , G06F21/87
CPC classification number: H01L23/573 , G06F21/75 , G06F21/79 , H01L23/5223 , H01L23/576 , H01L29/7883 , H10B41/35 , G06F21/87
Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
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公开(公告)号：US11651064B2
公开(公告)日：2023-05-16
申请号：US16832966
申请日：2020-03-27
Inventor： Michael Peeters , Fabrice Marinet
CPC classification number: G06F21/44 , G06F7/57 , G06F9/3818
Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.
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公开(公告)号：US11328098B2
公开(公告)日：2022-05-10
申请号：US16894523
申请日：2020-06-05
Applicant: STMICROELECTRONICS (ROUSSET) SAS
Inventor： Fabrice Marinet
Abstract: An electronic circuit includes an interface, a read-only memory in which encrypted data are stored, and cryptographic circuitry coupled to the interface. In operation, the cryptographic circuitry uses a decryption key received via the interface to decrypt the encrypted data. The electronic circuit performs one or more operations using the decrypted data.
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公开(公告)号：US11003595B2
公开(公告)日：2021-05-11
申请号：US16841403
申请日：2020-04-06
Inventor： Michael Peeters , Fabrice Marinet , Jean-Louis Modave
Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
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Patent Agency Ranking
公开(公告)号：US10585738B2
公开(公告)日：2020-03-10
申请号：US14996107
申请日：2016-01-14
Inventor： Fabrice Marinet , Jean-Louis Modave , Gilles Van Assche , Ronny Van Keer
Abstract: The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.
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17.发明授权公开(公告)号：US10579832B2
公开(公告)日：2020-03-03
申请号：US16200370
申请日：2018-11-26
Inventor： Jean-Louis Modave , Fabrice Marinet , Denis Farison
Abstract: A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device.
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18.发明授权公开(公告)号：US09870489B2
公开(公告)日：2018-01-16
申请号：US14970161
申请日：2015-12-15
Inventor： Jean-Louis Modave , Fabrice Marinet , Denis Farison
Abstract: A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device.
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公开(公告)号：US20140191578A1
公开(公告)日：2014-07-10
申请号：US14147814
申请日：2014-01-06
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jimmy Fort , Fabrice Marinet
IPC: G05F1/46
CPC classification number: G05F1/462 , G06F1/26 , G06F1/3237 , G06F21/755 , Y02D10/128 , Y10T307/549
Abstract: The current signature of an electronic function is masked by controlling a current source that supplies power for the electronic function is controlled in a dynamically-varying manner. Excess current is detected and compared to a threshold. If the detected excess current meets the threshold, the operation of the electronic function is modified, for example by controlling a clock.
Abstract translation: 通过控制以动态变化的方式控制为电子功能供电的电流源，屏蔽电子功能的当前签名。 检测到过多的电流并将其与阈值进行比较。 如果检测到的过电流满足阈值，则例如通过控制时钟来修改电子功能的操作。
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公开(公告)号：US12125808B2
公开(公告)日：2024-10-22
申请号：US18206923
申请日：2023-06-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Pascal Fornara , Fabrice Marinet
IPC: H01L29/788 , G06F21/75 , G06F21/79 , H01L23/00 , H01L23/522 , H10B41/35 , G06F21/87
CPC classification number: H01L23/573 , G06F21/75 , G06F21/79 , H01L23/5223 , H01L23/576 , H01L29/7883 , H10B41/35 , G06F21/87
Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
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