Display device and method of fabricating the same

    公开(公告)号:US11894355B2

    公开(公告)日:2024-02-06

    申请号:US17471581

    申请日:2021-09-10

    CPC classification number: H01L25/167 H01L27/124 H01L27/1259

    Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.

    Display device and method for fabricating the same

    公开(公告)号:US11765947B2

    公开(公告)日:2023-09-19

    申请号:US17107638

    申请日:2020-11-30

    CPC classification number: H10K59/131 H10K59/122 H10K59/1201

    Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.

    Display device
    13.
    发明授权

    公开(公告)号:US11271015B2

    公开(公告)日:2022-03-08

    申请号:US16876984

    申请日:2020-05-18

    Abstract: A display device includes a substrate, a buffer layer disposed on the substrate, a first semiconductor layer disposed on the buffer layer and including an oxide semiconductor and a first active layer, a first gate insulating layer disposed on the first semiconductor layer and the buffer layer, a second semiconductor layer disposed on the first gate insulating layer and including an oxide semiconductor, a second active layer, and a first oxide layer on the first active layer, a second gate insulating layer disposed on the second semiconductor layer, a first conductive layer disposed on the second gate insulating layer, an insulating layer disposed on the first conductive layer, a second conductive layer disposed on the insulating layer, a passivation layer disposed on the second conductive layer, and a third conductive layer disposed on the first passivation layer.

    Display device and method for fabricating the same

    公开(公告)号:US12069918B2

    公开(公告)日:2024-08-20

    申请号:US18230281

    申请日:2023-08-04

    CPC classification number: H10K59/131 H10K59/122 H10K59/1201

    Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.

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