公开(公告)号：US20230154527A1

公开(公告)日：2023-05-18

申请号：US17852035

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNJIN SONG ,  KYOUNGTAE KANG ,  SANGLOK KIM ,  CHIWEON YOON ,  BYUNGHOON JEONG

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4094

Abstract: A data transfer circuit in a nonvolatile memory device includes first repeaters, second repeaters and signal lines. The signal lines connect the first repeaters and the second repeaters, and include a first group of signal lines and a second group of signal lines alternatingly arranged. The first repeaters include a first group of repeaters activated in a first operation mode and a second group of repeaters activated in a second operation mode. The second repeaters include a third group of repeaters activated in the first operation mode and are connected to the first group of repeaters through the first group of signal lines floated in the second operation mode, and a fourth group of repeaters activated in the second operation mode and are connected to the second group of repeaters through the second group of signal lines floated in the first operation mode.

公开(公告)号：US20220011974A1

公开(公告)日：2022-01-13

申请号：US17168620

申请日：2021-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEONKYOO LEE ,  JEONGDON IHM ,  CHIWEON YOON ,  BYUNGHOON JEONG

IPC: G06F3/06 ,  G06F13/16 ,  G06F1/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.

公开(公告)号：US20180366199A1

公开(公告)日：2018-12-20

申请号：US16049863

申请日：2018-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

IPC: G11C16/08 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0483

Abstract: A nonvolatile memory device includes a memory cell array having a first plane and a second plane and an address decoder connected to the first plane through first string select lines and connected to the second plane through second string select line. The address decoder provides a string select signal and a string unselect signal to the first and second string select lines. The address decoder independently provides the string select signal and the string unselect signal to the first and second string select lines in each plane based on different string select line addresses corresponding to the first and second planes.

公开(公告)号：US20180068728A1

公开(公告)日：2018-03-08

申请号：US15806543

申请日：2017-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI-SANG LEE ,  DONGHUN KWAK ,  DAESEOK BYEON ,  CHIWEON YOON

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G11C16/24

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26

Abstract: A nonvolatile memory includes a memory cell array, a row decoder circuit, and a page buffer circuit. The row decoder circuit applies a turn-on voltage to string selection lines, which are connected to string selection transistors of a selected memory block, at a first precharge operation in response to a write command received from an external device. The page buffer circuit applies, in response to the write command, a first voltage to bit lines, which are connected to the string selection transistors, through a first precharge circuit at the first precharge operation regardless of loaded data and applies the first voltage and a second voltage to the bit lines through a second precharge circuit at a second precharge operation based on the loaded data. During the first precharge operation, write data is loaded onto the page buffer circuit.