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公开(公告)号：US20240072773A1
公开(公告)日：2024-02-29
申请号：US18331223
申请日：2023-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： DAEHOON NA , SEONKYOO LEE , SEUNGJUN BAE , TAESUNG LEE
CPC classification number: H03K3/013 , G06F13/1668 , G11C7/1093 , G11C7/222 , H03K3/017 , G06F2213/16
Abstract: An equalizer includes a first pulse width controller that is configured to generate a first signal by increasing a first pulse width of a first data signal having a first logic level, the first data signal corresponding to a current data bit, a second pulse width controller that is configured to generate a second signal by increasing a second pulse width of the first data signal having a second logic level, a first sampler that is configured to generate a first sampled signal by sampling the first signal, a second sampler that is configured to generate a second sampled signal by sampling the second signal, and a multiplexer that is configured to output the first sampled signal or the second sampled signal based on a value of a previous data bit.
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公开(公告)号：US20240393981A1
公开(公告)日：2024-11-28
申请号：US18793984
申请日：2024-08-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONKYOO LEE , JEONGDON IHM , CHIWEON YOON , BYUNGHOON JEONG
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US20220011974A1
公开(公告)日：2022-01-13
申请号：US17168620
申请日：2021-02-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONKYOO LEE , JEONGDON IHM , CHIWEON YOON , BYUNGHOON JEONG
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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4.发明公开公开(公告)号：US20240223187A1
公开(公告)日：2024-07-04
申请号：US18381611
申请日：2023-10-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Younggyu Lee , TONGSUNG KIM , SEUNGJUN BAE , SEONKYOO LEE , TAESUNG LEE
IPC: H03K19/00 , H03K19/017 , H03K19/17784
CPC classification number: H03K19/0005 , H03K19/01721 , H03K19/17784
Abstract: A semiconductor memory device may include an impedance adjustment pad, a dummy pull-down driver and an external resistor connected in parallel between the impedance adjustment pad and a ground, a recursive code generation circuit configured to recursively generate a pull-up code and a pull-down code corresponding to a target resistance by using the external resistor and the dummy pull-down driver as a reference resistance, in an impedance calibration operation of the semiconductor memory device, a code register configured to store the generated pull-up code and the pull-down code, and a calibration control logic circuit configured to control the recursive code generation circuit during a plurality of steps in the impedance calibration operation while adjusting a resistance value of the dummy pull-down driver.
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公开(公告)号：US20220101895A1
公开(公告)日：2022-03-31
申请号：US17477931
申请日：2021-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： YOUNGMIN JO , Byunghoon Jeong , TONGSUNG KIM , CHIWEON YOON , SEONKYOO LEE
IPC: G11C7/10
Abstract: A memory device includes a memory cell array, a page buffer, a control logic circuit, a plurality of input/output pins, a data bus inversion (DBI) pin, and an interface circuit. The page buffer is connected to the memory cell array. The control logic circuit is configured to control an operation of the memory cell array. The plurality of input/output pins receive a plurality of data signals from the controller. The DBI pin receives a DBI signal from the controller. The interface circuit count a first number of bits having a logic value of 1 and a second number of bits having a logic value of 0 from the data signals and the DBI signal and provide the data signals to the page buffer or the control logic circuit based on the first number and the second number.
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Patent Agency Ranking
公开(公告)号：US20230342085A1
公开(公告)日：2023-10-26
申请号：US18217063
申请日：2023-06-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONKYOO LEE , JEONGDON IHM , CHIWEON YOON , BYUNGHOON JEONG
CPC classification number: G06F3/0659 , G06F1/06 , G06F3/0613 , G06F3/0679 , G06F13/1668 , G11C16/0483 , G11C16/10 , G11C16/26
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US20220291871A1
公开(公告)日：2022-09-15
申请号：US17828176
申请日：2022-05-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： SEONKYOO LEE , JEONGDON IHM , CHIWEON YOON , BYUNGHOON JEONG
Abstract: A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.
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公开(公告)号：US20210349660A1
公开(公告)日：2021-11-11
申请号：US17030635
申请日：2020-09-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： TONGSUNG KIM , JANGWOO LEE , SEONKYOO LEE , CHIWEON YOON , JEONGDON IHM
Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.
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公开(公告)号：US20200220244A1
公开(公告)日：2020-07-09
申请号：US16730277
申请日：2019-12-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jindo BYUN , SEONKYOO LEE , HYUNJIN KIM
IPC: H01P3/08 , G11C16/10 , H01L23/538
Abstract: A multi-mode transmission line includes a first and second conductive layers, first and second waveguide walls, a strip line, and a blind conductor. The second conductive layer that is formed over the first conductive layer. The first waveguide wall is elongated in a first direction and is in contact with the first conductive layer and the second conductive layer in a vertical direction. The second waveguide wall is elongated in the first direction parallel to the first waveguide wall and is in contact with the first conductive layer and the second conductive layer in the vertical direction. The strip line is formed between the first and second conductive layers and between the first and second waveguide walls. The blind conductor is connected to one of the first conductive layer, the second conductive layer, the first waveguide wall, or the second waveguide wall.
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10.发明申请SEMICONDUCTOR MEMORY SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE 有权半导体存储器系统，半导体存储器件和操作半导体存储器件的方法公开(公告)号：US20170053683A1
公开(公告)日：2017-02-23
申请号：US15198564
申请日：2016-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SEONKYOO LEE , TAESUNG LEE , JEONGDON IHM , BYUNGHOON JEONG
CPC classification number: G11C7/22 , G06F11/10 , G11C7/106 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C16/32
Abstract: A semiconductor device of the inventive concept includes a timing circuit configured to receive a first timing signal of a first pulse width from an external device and output a second timing signal having a pulse width which is gradually being reduced from a second pulse width longer than the pulse width of the first timing signal, and a data input/output circuit receiving the second timing signal and outputting data to the external device in synchronization with the second timing signal.
Abstract translation: 本发明构思的半导体器件包括：定时电路，被配置为从外部设备接收第一脉冲宽度的第一定时信号，并输出第二定时信号，该第二定时信号具有从第二脉冲宽度逐渐减小的脉冲宽度 第一定时信号的脉冲宽度和接收第二定时信号的数据输入/输出电路，并且与第二定时信号同步地将数据输出到外部设备。
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