公开(公告)号：US20240241694A1

公开(公告)日：2024-07-18

申请号：US18355046

申请日：2023-07-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daekun YOON ,  Soon-Wan KWON ,  Seok Ju YUN ,  Jaehyuk LEE ,  Dong-Jin CHANG

IPC: G06F7/544 ,  G06F7/501 ,  G11C7/10

CPC classification number: G06F7/5443 ,  G06F7/501 ,  G11C7/1012

Abstract: Disclosed is an in-memory computing device and method. The in-memory computing device includes: a memory unit including bit cells configured to store first input data having a reference-bit-count, receive second input data also having the reference-bit-count, and perform a multiplication operation between the first input data and the second input data; and an operation unit including: a first adder tree configured to output intermediate operation results by adding results of performing the multiplication operation output with respect to each of the bit cells; a branch module configured to branch the intermediate operation results according to an operation mode of the in-memory computing device; and a second adder tree configured to output a final operation result based on an output of the branch module.

公开(公告)号：US20240094988A1

公开(公告)日：2024-03-21

申请号：US18117597

申请日：2023-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Jin CHANG ,  Sungmeen MYUNG ,  Jaehyuk LEE ,  Daekun YOON ,  Seok Ju YUN

IPC: G06F7/544 ,  G06F7/40

CPC classification number: G06F7/5443 ,  G06F7/405

Abstract: A multi-bit accumulator including a plurality of 1-bit Wallace trees configured to perform an add operation on single-bit input data, a plurality of tristate buffers configured to output a result of the add operation of the 1-bit Wallace trees, according to an enable signal, and a shift-adder configured to perform an accumulation operation on the result of the add operation of the plurality of 1-bit Wallace trees by a shift operation based on a clock signal.

公开(公告)号：US20240028298A1

公开(公告)日：2024-01-25

申请号：US18185461

申请日：2023-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaehyuk LEE ,  Seok Ju YUN ,  Dong-Jin CHANG ,  Sungmeen MYUNG ,  Daekun YOON

IPC: G06F7/544 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

CPC classification number: G06F7/5443 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419

Abstract: A memory device performs a multiplication operation using a multiplying cell including a memory cell and a switching element, in which the memory cell includes a pair of inverters connected to each other in opposite directions, a first transistor connected to one end of the pair of inverters, and a second transistor connected to the other end of the pair of inverters, and has a set weight; and the switching element is connected to an output end of the memory cell and configured to perform switching in response to an input value and output a signal corresponding to a multiplication result between the input value and the weight.

公开(公告)号：US20230170026A1

公开(公告)日：2023-06-01

申请号：US17880849

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Ju YUN ,  Daekun YOON ,  Sang Joon KIM ,  Seungchul JUNG

IPC: G11C16/10 ,  G11C16/32 ,  G11C16/20 ,  G11C29/52

CPC classification number: G11C16/102 ,  G11C16/32 ,  G11C16/20 ,  G11C29/52

Abstract: Provided is method and apparatus with memory array programming. A memory apparatus may include a memory array including memory cells, and a memory controller, where the memory controller is configured to configured to repeat, for a plurality of times, a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell, a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error, and a programming of a select one of the first and second memory cells that has the greatest present time current error.