公开(公告)号：US20250126835A1

公开(公告)日：2025-04-17

申请号：US18625457

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin LEE ,  Min Tae RYU ,  Younggeun SONG ,  Sanghoon AHN ,  Min Hee CHO ,  Daewon HA

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device may include peripheral circuit structures on a substrate, an interlayer insulating layer on the peripheral circuit structure, a bit line extending in a first direction in the interlayer insulating layer, a semiconductor pattern on the bit line, and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other, first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively, and a gate insulating pattern interposed between the first vertical portion and the first word line, and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

公开(公告)号：US20240422964A1

公开(公告)日：2024-12-19

申请号：US18421187

申请日：2024-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Wonsok LEE ,  Juho LEE ,  Daewon HA

IPC: H10B12/00 ,  H01L29/10

Abstract: A semiconductor memory device includes a memory cell array having a three-dimensional structure, the memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction are perpendicular to each other, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, wherein each of the plurality of memory cells includes two transistors including at a least portions of two word lines passing through the memory cell in the vertical direction and at least portions of two bit lines respectively on both sides of the two word lines in the first lateral direction, each of the two bit line extending along the second lateral direction, and each of the plurality of memory cells does not include a capacitor.

公开(公告)号：US20240266287A1

公开(公告)日：2024-08-08

申请号：US18457907

申请日：2023-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Daewon HA

IPC: H01L23/528 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20

CPC classification number: H01L23/5283 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20

Abstract: A semiconductor device may include first conductive lines spaced apart from each other in a first direction on a substrate, second conductive lines spaced apart from the first conductive lines in a second direction, a gate electrode between the first and second conductive lines and extending in the first direction, a first selection gate electrode between the first conductive lines and the gate electrode and extending in the first direction, a plurality of channel patterns surrounding a side surface of the gate electrode and spaced apart from each other in the first direction, a plurality of first selection channel patterns surrounding a side surface of the first selection gate electrode and a ferroelectric pattern between the gate electrode and each of the channel patterns. The first selection channel patterns may be spaced apart from each other in the first direction and connected to the channel patterns, respectively.

公开(公告)号：US20240164108A1

公开(公告)日：2024-05-16

申请号：US18235000

申请日：2023-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyunghwan LEE ,  Yongseok KIM ,  Daewon HA

IPC: H10B51/20 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10

Abstract: A three-dimensional ferroelectric memory device includes a channel on a substrate and extending in a vertical direction substantially perpendicular to an upper surface of the substrate, a gate insulation pattern and a conductive pattern stacked on and surrounding a sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate, a ferroelectric pattern contacting a portion of an outer sidewall of the conductive pattern, a gate electrode contacting the ferroelectric pattern, and first and second source/drain patterns contacting lower and upper surfaces, respectively, of the channel.

公开(公告)号：US20240049472A1

公开(公告)日：2024-02-08

申请号：US18208943

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiheun LEE ,  Yongseok KIM ,  Hyuncheol KIM ,  Daewon HA

IPC: H10B51/20 ,  H10B51/10 ,  H01L29/78 ,  H01L29/51 ,  H01L29/18

CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/18

Abstract: A ferroelectric memory device includes a channel layer, a gate insulation layer on the channel layer, and a gate electrode layer on the gate insulation layer. The gate insulation layer includes a ferroelectric inductive layer and a ferroelectric stack structure on the ferroelectric inductive layer, and the ferroelectric stack structure is stacked in an order or reverse order of a ferroelectric layer and a non-ferroelectric layer.

公开(公告)号：US20230307448A1

公开(公告)日：2023-09-28

申请号：US17950434

申请日：2022-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan LEE ,  Sungil PARK ,  Jae Hyun PARK ,  Daewon HA

IPC: H01L27/06 ,  H01L21/822 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/785

Abstract: A three-dimensional semiconductor device comprises a first active region on a substrate and including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region and including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a first active contact electrically connected to the lower source/drain pattern, an upper separation structure between the first active contact and the upper source/drain pattern, a second active contact electrically connected to the upper source/drain pattern, and a lower separation structure between the second active contact and the lower source/drain pattern.

公开(公告)号：US20230276634A1

公开(公告)日：2023-08-31

申请号：US18069398

申请日：2022-12-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon HA ,  Kyunghwan Lee

IPC: H10B51/30 ,  H10B51/40 ,  G11C11/22 ,  H01L29/51

CPC classification number: H10B51/30 ,  H10B51/40 ,  G11C11/2275 ,  H01L29/516

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction, a gate electrode on the substrate and extending in a second direction, and a plurality of channel layers on the active region. The plurality of channel layers are spaced apart from each other in a third direction perpendicular to an upper surface of the substrate. The device includes a plurality of dielectric layers between the plurality of channel layers and the gate electrode, the plurality of dielectric layers include at least one of a ferroelectric material or an anti-ferroelectric material, and each of the plurality of dielectric layers has a different coercive voltage. The device includes source/drain regions in recess regions in which the active region is recessed, the source/drain regions are on both sides of the gate electrode, and the source/drain regions are in contact with the plurality of channel layers.

公开(公告)号：US20230052477A1

公开(公告)日：2023-02-16

申请号：US17719723

申请日：2022-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daewon HA ,  Mingyu KIM ,  Doyoung CHOI

IPC: H01L27/11 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor device comprises an active pattern on a substrate, a pair of first source/drain patterns on the active pattern, a pair of second source/drain patterns on top surfaces of the first source/drain patterns, a gate electrode extending across the active pattern and having sidewalls that face the first and second source/drain patterns, a first channel structure extending across the gate electrode and connecting the first source/drain patterns, and a second channel structure extending across the gate electrode and connecting the second source/drain patterns. The gate electrode includes a first lower part between a bottom surface of the first channel structure and a top surface of the active pattern, and a first upper part between a top surface of the first channel structure and a bottom surface of the second channel structure. The first lower part has a thickness greater than that of the first upper part.

公开(公告)号：US20220416045A1

公开(公告)日：2022-12-29

申请号：US17583314

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil PARK ,  Jae Hyun PARK ,  Kyungho KIM ,  Cheoljin YUN ,  Daewon HA

IPC: H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20220399463A1

公开(公告)日：2022-12-15

申请号：US17724619

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon KIM ,  Doyoung CHOI ,  Daewon HA ,  Mingyu KIM

IPC: H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a plurality of source/drain patterns in a first direction on the active pattern, a first channel structure between a pair of source/drain patterns, a second channel structure between another pair of source/drain patterns, a first gate electrode extending in a second direction perpendicular to the first direction, and a second gate electrode intersecting the second channel structure and extending in the second direction. The first gate electrode includes a first portion between a bottom surface of the first channel structure and a top surface of the active pattern, and the second gate electrode includes a first portion between a bottom surface of the second channel structure and the top surface of the active pattern. A thickness of the first portion of the second gate electrode is greater than a thickness of the first portion of the first gate electrode.