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公开(公告)号：US20230095830A1
公开(公告)日：2023-03-30
申请号：US17834240
申请日：2022-06-07
发明人： Hyo-Jin KIM , Daewon HA
IPC分类号： H01L29/78 , H01L29/417
摘要： Disclosed are three-dimensional semiconductor device and their fabrication methods. The device includes a first active region on a substrate and including a first source/drain pattern and a first channel pattern connected to the first source/drain pattern, a first active contact on the first source/drain pattern, a second active region on the first active region and the first active contact and including a second source/drain pattern and a second channel pattern connected to the second source/drain pattern, a second active contact on the second source/drain pattern, a gate electrode that vertically extends from the first channel pattern toward the second channel pattern, a first power line and a second power line that are below the first active region, and a first metal layer on the gate electrode and the second active contact.
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公开(公告)号：US20240120401A1
公开(公告)日：2024-04-11
申请号：US18390246
申请日：2023-12-20
发明人： Sungil PARK , Jae Hyun PARK , Kyungho KIM , Cheoljin YUN , Daewon HA
IPC分类号： H01L29/423 , H01L29/786
CPC分类号： H01L29/42392 , H01L29/78618 , H01L29/78696
摘要： A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.
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公开(公告)号：US20140332863A1
公开(公告)日：2014-11-13
申请号：US14248594
申请日：2014-04-09
发明人： JaeHoo PARK , Daewon HA , Uihui KWON , Sung-Dae SUK
CPC分类号： H01L29/785 , H01L27/092 , H01L29/66795 , H01L29/7853
摘要： Provided are a semiconductor device and a method of manufacturing the same. The method of manufacturing a semiconductor device includes forming an active fin on a substrate; oxidizing a portion of the active fin to form an insulating pattern between the active fin and the substrate; forming a first gate pattern on the substrate, wherein the first gate pattern crosses the active fin; exposing the substrate on both sides of the first gate pattern; and forming source/drain regions on the exposed substrate.
摘要翻译： 提供半导体器件及其制造方法。 制造半导体器件的方法包括：在衬底上形成有源散热片; 氧化活性鳍片的一部分以在活性鳍片和衬底之间形成绝缘图案; 在所述衬底上形成第一栅极图案，其中所述第一栅极图案与所述有源鳍片交叉; 在第一栅极图案的两侧上暴露衬底; 以及在暴露的衬底上形成源极/漏极区域。
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公开(公告)号：US20230371270A1
公开(公告)日：2023-11-16
申请号：US18315181
申请日：2023-05-10
发明人： Hyuncheol KIM , Yongseok KIM , Kiheun LEE , Daewon HA
CPC分类号： H10B51/30 , H10B51/10 , H01L29/40111
摘要： A memory device may include a channel region, a conductive electrode disposed on the channel region, and a data storage structure disposed between the channel region and the conductive electrode. The data storage structure includes a first dielectric layer and a second dielectric layer disposed on the first dielectric layer, the second dielectric layer includes a ferroelectric region and a barrier dielectric region on the ferroelectric region, the ferroelectric region includes a first material, and the barrier dielectric region includes a second material formed by nitriding or oxidizing the first material.
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公开(公告)号：US20230074880A1
公开(公告)日：2023-03-09
申请号：US17830884
申请日：2022-06-02
发明人： Sungil PARK , Jaehyun PARK , Hyo-Jin KIM , Hyojin KIM , Daewon HA
IPC分类号： H01L27/06 , H01L29/06 , H01L29/08 , H01L29/423 , H01L29/786 , H01L29/775 , H01L29/417 , H01L29/735 , H01L21/02 , H01L29/66 , H01L21/8249
摘要： A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity. The third structure includes third lower and upper impurity regions having the second-type conductivity, the third upper impurity region having an impurity concentration higher than a that of the third lower impurity region.
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公开(公告)号：US20220223711A1
公开(公告)日：2022-07-14
申请号：US17388584
申请日：2021-07-29
发明人： Sungmin KIM , Daewon HA
IPC分类号： H01L29/49 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/02 , H01L29/66
摘要： A semiconductor device includes a plurality of active regions on a substrate. A gate electrode is on, and intersects, the active regions. A plurality of source/drain regions are on the active regions, such that the source/drain regions are adjacent to opposite sides of the gate electrode and the gate electrode is between the source/drain regions. A separation structure is between adjacent source/drain regions. The separation structure includes an insulating pattern and a spacer layer. The insulating pattern includes first and second side surfaces that are opposite side surfaces of the insulating pattern and are adjacent to separate, respective source/drain regions. The spacer layer is on the first and second side surfaces. An uppermost end of the insulating pattern is farther from a lower surface of the substrate than a first upper surface of the spacer layer that is adjacent to the first and second side surfaces.
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公开(公告)号：US20240250169A1
公开(公告)日：2024-07-25
申请号：US18420969
申请日：2024-01-24
发明人： KYUNGHWAN LEE , Sanghoon UHM , Minhee CHO , Daewon HA
CPC分类号： H01L29/7827 , H10B12/0335 , H10B12/053 , H10B12/34 , H10B12/482
摘要： A semiconductor device includes an active pattern having a vertical active portion extending in a vertical direction and a first bend portion bent from an upper region of the vertical active portion; a gate electrode spaced apart from the active pattern, wherein at least a portion thereof faces the vertical active portion; an etch stop layer in which at least a portion thereof is disposed between an upper surface of the gate electrode and the first bend portion; a dielectric layer in which at least a portion thereof is disposed between the active pattern and the gate electrode; and a contact plug disposed on the etch stop layer and at least penetrating through the first bend portion.
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公开(公告)号：US20230380176A1
公开(公告)日：2023-11-23
申请号：US18102349
申请日：2023-01-27
发明人： Daewon HA , Kyunghwan LEE , Youngnam Hwang
摘要： A semiconductor device includes a cell region including a plurality of memory cells, and a peripheral circuit region controlling the plurality of memory cells. Each of the plurality of memory cells includes a first active region and a second active region adjacent to each other, a first channel layer and a second channel layer extending in the first direction, connected to the first active region and the second active region, and separated from each other in the third direction, a first ferroelectric layer and a first gate electrode layer sequentially provided on the first channel layer, and a second ferroelectric layer and a second gate electrode layer sequentially provided on the second channel layer. The first gate electrode layer and the second gate electrode layer are separated from each other in the third direction.
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公开(公告)号：US20230292522A1
公开(公告)日：2023-09-14
申请号：US18055974
申请日：2022-11-16
发明人： Daewon HA , Kyunghwan LEE , Hyunmog PARK
IPC分类号： H01L21/02
摘要： A three-dimensional non-volatile memory device includes a memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction on a substrate. The first lateral direction and the second lateral direction are parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell array includes a plurality of horizontal channel regions and a vertical word line. The plurality of horizontal channel regions extend in the first lateral direction on the substrate. The plurality of horizontal channel regions overlap each other and are apart from each other in the vertical direction. The vertical word line passes through the plurality of horizontal channel regions in the vertical direction.
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公开(公告)号：US20230180453A1
公开(公告)日：2023-06-08
申请号：US18054986
申请日：2022-11-14
发明人： Hyuncheol KIM , Yongseok KIM , Kyunghwan LEE , Minjun LEE , Daewon HA
IPC分类号： H01L27/108
CPC分类号： H01L27/10802
摘要： A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.
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