公开(公告)号：US11764149B2

公开(公告)日：2023-09-19

申请号：US17866782

申请日：2022-07-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suhyun Bark ,  Kyeongbeom Park ,  Jongmin Baek ,  Jangho Lee ,  Wookyung You ,  Deokyoung Jung

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/088

Abstract: A semiconductor device includes transistors on a substrate, a first interlayer insulating layer on the transistors, a lower interconnection line in an upper portion of the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, an upper interconnection line in the second interlayer insulating layer, the upper interconnection line including a via portion penetrating the etch stop layer to contact the lower interconnection line, and an etch stop pattern on the etch stop layer and in contact with a first sidewall of the via portion. The second interlayer insulating layer extends on the etch stop pattern and a top surface of the etch stop layer free of the etch stop pattern. A dielectric constant of the etch stop pattern is higher than a dielectric constant of the etch stop layer.

公开(公告)号：US11721622B2

公开(公告)日：2023-08-08

申请号：US17453197

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junghoo Shin ,  Sanghoon Ahn ,  Seung Jae Lee ,  Deokyoung Jung ,  Woojin Lee

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53204

Abstract: A semiconductor device includes a second insulating layer disposed on a substrate and that includes a first trench that extends in a first direction, a first via disposed in the first hole, a first interconnection layer disposed in the first trench on the first via and that has an upwardly upper region, and a third insulating layer disposed on the second insulating layer and that includes a second hole and a second trench connected to the second hole. The first trench has inclined side surfaces such that a width of the first trench increases in a direction toward the substrate, the second hole has inclined side surfaces such that a width of the second hole decreases in the direction toward the substrate, and a lower portion of the second hole is wider than an upper surface of the first interconnection layer.

公开(公告)号：US10199325B2

公开(公告)日：2019-02-05

申请号：US15792911

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin Yim ,  Jongmin Baek ,  Deokyoung Jung ,  Kyuhee Han ,  Byunghee Kim ,  Jiyoung Kim ,  Naein Lee ,  Sangshin Jang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

公开(公告)号：US20160163590A1

公开(公告)日：2016-06-09

申请号：US14956869

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung Jung ,  Seong-Min Son ,  Jin-Ho An ,  Byung-Lyul Park ,  Ji-Soon Park ,  Ho-Jin Lee

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L24/03 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/114 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599

Abstract: Disclosed is a method of manufacturing a semiconductor device. A preliminary wafer-carrier assembly is formed in such a way that a wafer structure having a plurality of via structures is adhered to a light-penetrating carrier by a photodegradable adhesive. A wafer-carrier assembly having an optical shielding layer for inhibiting or preventing a light penetration is formed such that the wafer structure, the carrier and the adhesive are covered with the optical shielding layer except for the backside of the wafer structure through which the via structures are exposed. An interconnector is formed on the backside of the wafer structure such that the via structures make contact with the interconnector, and the wafer structure and the carrier are separated from each other by irradiating a light to the wafer-carrier assembly. Accordingly, the adhesive is inhibited or prevented from being dissolved during a plasma process on the wafer-carrier assembly.

Abstract translation: 公开了半导体器件的制造方法。 初步的晶片载体组件形成为具有多个通路结构的晶片结构通过可光降解的粘合剂粘附到透光载体上。 形成具有用于抑制或防止光穿透的光学屏蔽层的晶片载体组件，使得晶片结构，载体和粘合剂被除了晶片结构的背面之外的光学屏蔽层覆盖，通过该晶片结构， 被暴露。 在晶片结构的背面形成互连器，使得通孔结构与互连器接触，并且通过向晶片载体组件照射光而使晶片结构和载体彼此分离。 因此，在晶片载体组件的等离子体处理中，粘合剂被抑制或防止溶解。