公开(公告)号：US09520168B2

公开(公告)日：2016-12-13

申请号：US15151687

申请日：2016-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donghun Kwak ,  Hyun Jun Yoon ,  Dongkyo Shim

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1063 ,  G11C16/0483 ,  G11C16/26

Abstract: A nonvolatile memory device includes a cell array including a plurality of cell strings extending on a substrate in a vertical direction, a page buffer connected to a plurality of bit lines and configured to store sensing data of the cell array in a sensing operation, a voltage generator configured to provide voltages to a plurality of word lines and the plurality of bit lines, and an input/output buffer configured to temporarily store the sensing data received in a data dump from the page buffer and to output the temporarily stored data to an external device. The nonvolatile memory device further includes control logic configured to set a status of the nonvolatile memory device to a ready state after the sensing data is dumped to the input/output buffer and before recovery of the cell array from a bias voltage of the sensing operation is complete.

Abstract translation: 一种非易失性存储器件，包括一个单元阵列，该单元阵列包括在垂直方向上在基片上延伸的多个单元串，连接到多个位线的一个页缓冲器，并且被配置为在感测操作中存储该单元阵列的感测数据， 发生器，其被配置为向多个字线和所述多个位线提供电压;以及输入/输出缓冲器，被配置为临时存储从所述页缓冲器接收的数据转储中的感测数据，并将所述临时存储的数据输出到外部 设备。 非易失性存储装置还包括控制逻辑，其被配置为在将感测数据转储到输入/输出缓冲器之后并且在从感测操作的偏置电压恢复单元阵列之前将非易失性存储器件的状态设置为就绪状态 完成。

公开(公告)号：US11854623B2

公开(公告)日：2023-12-26

申请号：US17520276

申请日：2021-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Dongkyo Shim

IPC: G11C16/16 ,  G06F12/02 ,  G06F3/06 ,  G11C16/34

CPC classification number: G11C16/16 ,  G06F3/064 ,  G06F12/0246 ,  G11C16/3431 ,  G11C16/3436 ,  G06F3/0679 ,  G06F2212/7211

Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.

公开(公告)号：US20230153001A1

公开(公告)日：2023-05-18

申请号：US18053919

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyo Shim ,  Sang Soo Park

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

Abstract: Disclosed is a nonvolatile memory device which includes a first plane that includes a plurality of memory blocks, a second plane that includes a plurality of memory blocks, an address replacing circuit that receives a first input address from an external controller, the first input address corresponding to a first memory block of the plurality of memory blocks of the first plane from an external controller and outputs a replaced address based on the first input address and bad block information, and an address decoder that controls word lines connected with a second memory block based on the replaced address, the word lines corresponding to the replaced address from among the plurality of memory blocks of the second plane. The first memory block of the first plane is a bad block.

公开(公告)号：US11183250B2

公开(公告)日：2021-11-23

申请号：US16661351

申请日：2019-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Dongkyo Shim

IPC: G11C16/16 ,  G06F12/02 ,  G06F3/06 ,  G11C16/34

Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. when the When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.

公开(公告)号：US10388367B2

公开(公告)日：2019-08-20

申请号：US15351552

申请日：2016-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Won Park ,  Dongkyo Shim ,  Kitae Park ,  Sang-Won Shim

IPC: G11C8/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C29/02

Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.

公开(公告)号：US09812214B2

公开(公告)日：2017-11-07

申请号：US15340957

申请日：2016-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkyo Shim ,  Sang-Soo Park

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C11/56 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/3445 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26

Abstract: A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.