公开(公告)号：US11316010B2

公开(公告)日：2022-04-26

申请号：US17038217

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Heon-jong Shin ,  In-chan Hwang ,  Jae-ran Jang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088

Abstract: An integrated circuit device is provided as follows. A fin-type active region extends on a substrate in a first horizontal direction. A gate line extends on the fin-type active region in a second horizontal direction intersecting the first horizontal direction. A source/drain region is disposed in the fin-type active region at one side of the gale line. An insulating cover extends parallel to the substrate, with the gate line and the source/drain region arranged between the insulating cover and the substrate. A source/drain contact that vertically extends through the insulating cover has a first sidewall covered with the insulating cover and an end connected to the source/drain region. A fin isolation insulating unit vertically extends through the insulating cover into the fin-type active region. The source/drain region is arranged between the fin isolation insulating unit and the gate line.

公开(公告)号：US11004788B2

公开(公告)日：2021-05-11

申请号：US16229781

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hwi-Chan Jun ,  Seul-Ki Hong ,  Hyun-Soo Kim ,  Sang-Hyun Lee

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/423 ,  H01L29/417

Abstract: A semiconductor device may include a plurality of active patterns and a plurality of gate structure on a substrate, a first insulating interlayer covering the active patterns and the gate structures, a plurality of first contact plugs extending through the first insulating interlayer, a plurality of second contact plugs extending through the first insulating interlayer, and a first connecting pattern directly contacting a sidewall of at least one contact plug selected from the first and second contact plugs. Each of gate structures may include a gate insulation layer, a gate electrode and a capping pattern. Each of first contact plugs may contact the active patterns adjacent to the gate structure. Each of the second contact plugs may contact the gate electrode in the gate structures. An upper surface of the first connecting pattern may be substantially coplanar with upper surfaces of the first and second contact plugs.

公开(公告)号：US20160307887A1

公开(公告)日：2016-10-20

申请号：US15196781

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hwi-Chan Jun

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/768 ,  H01L21/285 ,  H01L49/02 ,  H01L23/535

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53266 ,  H01L23/535 ,  H01L28/24 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括提供包括晶体管区域和电阻器区域的衬底，在电阻器区域中的衬底上形成伪栅极结构和下层间绝缘层; 形成具有缓冲绝缘图案的电阻器结构，电阻元件和顺序地设置在下层间绝缘层上的蚀刻延迟图案; 以及形成电阻器接触结构，其被配置为穿过所述蚀刻延迟图案并与所述电阻器元件接触。

公开(公告)号：US11380791B2

公开(公告)日：2022-07-05

申请号：US16225122

申请日：2018-12-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hyo-Jin Kim ,  Kyoung-Mi Park ,  Hwi-Chan Jun ,  Seung-Seok Ha

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

Abstract: A semiconductor device includes a first impurity region, a channel pattern, a second impurity region, a gate structure, a first contact pattern, a second contact pattern and a spacer. The first impurity region may be formed on a substrate. The channel pattern may protrude from an upper surface of the substrate. The second impurity region may be formed on the channel pattern. The gate structure may be formed on a sidewall of the channel pattern and the substrate adjacent to the channel pattern, and the gate structure may include a gate insulation pattern and a gate electrode. The first contact pattern may contact an upper surface of the second impurity region. The second contact pattern may contact a surface of the gate electrode. The spacer may be formed between the first and second contact patterns. The spacer may surround a portion of a sidewall of the second contact pattern, and the spacer may contact a sidewall of each of the first and second contact patterns.

公开(公告)号：US10886227B2

公开(公告)日：2021-01-05

申请号：US16217220

申请日：2018-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Jin Kim ,  Chang-Hwa Kim ,  Hwi-Chan Jun ,  Chui-Hong Park ,  Jae-Seok Yang ,  Kwan-Young Chun

IPC: H01L23/535 ,  H01L27/088 ,  H01L21/84 ,  H01L27/12 ,  H01L21/768 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device and a method of manufacturing a semiconductor device, the device including gate structures on a substrate; source/drain layers on portions of the substrate that are adjacent the gate structures, respectively; first contact plugs contacting upper surfaces of the source/drain layers, respectively; a second contact plug contacting one of the gate structures, a sidewall of the second contact plug being covered by an insulating spacer; and a third contact plug commonly contacting an upper surface of at least one of the gate structures and at least one of the first contact plugs, at least a portion of a sidewall of the third contact plug not being covered by an insulating spacer.

公开(公告)号：US09679991B2

公开(公告)日：2017-06-13

申请号：US14670324

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi-Chan Jun ,  Deok-Han Bae ,  Hyun-Seung Song ,  Seung-Seok Ha

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656

Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

公开(公告)号：US09406770B2

公开(公告)日：2016-08-02

申请号：US14668430

申请日：2015-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Seung Song ,  Hwi-Chan Jun

IPC: H01L21/8234 ,  H01L29/45 ,  H01L21/285 ,  H01L49/02 ,  H01L29/66 ,  H01L27/06 ,  H01L29/51

CPC classification number: H01L27/0629 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5228 ,  H01L23/53266 ,  H01L23/535 ,  H01L28/24 ,  H01L29/456 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.

Abstract translation: 提供一种制造半导体器件的方法。 该方法包括提供包括晶体管区域和电阻器区域的衬底，在电阻器区域中的衬底上形成伪栅极结构和下层间绝缘层; 形成具有缓冲绝缘图案的电阻器结构，电阻元件和顺序地设置在下层间绝缘层上的蚀刻延迟图案; 以及形成电阻器接触结构，其被配置为穿过所述蚀刻延迟图案并与所述电阻器元件接触。