公开(公告)号：US09876094B2

公开(公告)日：2018-01-23

申请号：US14984037

申请日：2015-12-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok-Han Bae ,  Kyung-Soo Kim ,  Chul-Sung Kim ,  Woo-Cheol Shin ,  Hwi-Chan Jun

IPC: H01L29/66 ,  H01L29/45 ,  H01L21/8234 ,  H01L21/285 ,  H01L23/485 ,  H01L21/768 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76865 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/485 ,  H01L29/41766 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a gate electrode and a source or drain disposed at opposite sides of the gate electrode, forming an interlayer insulating layer covering the gate electrode and the source or drain, forming a contact hole exposing the source or drain in the interlayer insulating layer, forming a silicide layer on a bottom surface of the contact hole, and forming a spacer on sidewalls of the contact hole and an upper surface of the silicide layer.

公开(公告)号：US20160380084A1

公开(公告)日：2016-12-29

申请号：US15234484

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONG-HYUK KIM ,  Kang-Ill Seo ,  Hyun-Jae Kang ,  Deok-Han Bae

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

公开(公告)号：US10593671B2

公开(公告)日：2020-03-17

申请号：US16013734

申请日：2018-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok-Han Bae ,  Sang-Young Kim ,  Byung-Chan Ryu ,  Jong-Ho You ,  Da-Un Jeon

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L29/78 ,  H01L21/311 ,  H01L29/165 ,  H01L21/306

Abstract: An integrated circuit device includes a substrate having a fin-type active region that extends in a first direction, a gate structure that intersects the fin-type active region on the substrate and extends in a second direction perpendicular to the first direction and parallel to an upper surface of the substrate, a guide pattern that extends on the gate structure in the second direction and has an inclined side surface that extends in the second direction, source/drain regions disposed on both sides of the gate structure, and a first contact that is electrically connected to one of the source/drain regions and in which an upper portion contacts the inclined side surface of the guide pattern. The width of an upper portion of the guide pattern in the first direction is less than the width of a lower portion of the guide pattern in the first direction.

公开(公告)号：US09318478B1

公开(公告)日：2016-04-19

申请号：US14610046

申请日：2015-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Deok-Han Bae ,  Dong-Kwon Kim ,  Jong-Hyuk Kim ,  Yoon-Moon Park

IPC: H01L27/088 ,  H01L27/02

CPC classification number: H01L27/0207 ,  H01L27/0886

Abstract: A semiconductor device includes a first dummy gate having a first width, a second dummy gate adjacent to the first dummy gate in a lengthwise direction and having a second width, and a first bridge connecting the first dummy gate and the second dummy gate to each other. The first width and the second width are smaller than a minimum processing line width.

Abstract translation: 半导体器件包括具有第一宽度的第一伪栅极和与第一虚设栅极相邻的具有第二宽度的第二伪栅极，以及将第一伪栅极和第二伪栅极彼此连接的第一桥接器 。 第一宽度和第二宽度小于最小处理线宽度。

公开(公告)号：US10038077B2

公开(公告)日：2018-07-31

申请号：US15234484

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyuk Kim ,  Kang-Ill Seo ,  Hyun-Jae Kang ,  Deok-Han Bae

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

公开(公告)号：US09679991B2

公开(公告)日：2017-06-13

申请号：US14670324

申请日：2015-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwi-Chan Jun ,  Deok-Han Bae ,  Hyun-Seung Song ,  Seung-Seok Ha

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/31144 ,  H01L21/76897 ,  H01L29/66545 ,  H01L29/6656

Abstract: Embodiments of the disclosure relate to a method for manufacturing a semiconductor device including a field effect transistor with improved electrical characteristics. According to embodiments of the disclosure, self-aligned contact plugs may be effectively formed using a metal hard mask portion disposed on a gate portion. In addition, a process margin of a photoresist mask for the formation of the self-aligned contact plugs may be improved by using the metal hard mask portion.

公开(公告)号：US09472653B2

公开(公告)日：2016-10-18

申请号：US14554107

申请日：2014-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyuk Kim ,  Kang-Ill Seo ,  Hyun-Jae Kang ,  Deok-Han Bae

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.

Abstract translation: 提供一种制造半导体器件的方法。 在基板上形成多个目标图案。 多个目标图案沿着第一方向彼此平行地延伸。 形成在第一方向上延伸并且包括多个第一开口的第一掩模图案。 形成沿与第一方向交叉的第二方向延伸并且包括多个第二开口的第二掩模图案。 每个第二开口与每个第一开口重叠以形成重叠的开口区域。 使用第一掩模图案和第二掩模图案作为蚀刻掩模，通过重叠的开口区域蚀刻多个目标图案的区域。 多个目标图案的区域与重叠的开口区域重叠。