公开(公告)号：US20250123920A1

公开(公告)日：2025-04-17

申请号：US18764870

申请日：2024-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yujung Song ,  Sung-Rae Kim ,  Hye-Ran Kim

IPC: G06F11/10

Abstract: A memory device and a method of operating the memory device are provided. The memory device includes a memory cell array including a plurality of memory cells to store data, an error correction code (ECC) circuit, and an error check and scrub (ECS) circuit. The ECC circuit reads the data from the memory cell array and corrects errors in the data. The ECS circuit performs a scrubbing operation on the memory cell array and transmits a signal for an error address detected based on the scrubbing operation to an external circuit and stores the error address which was transmitted.

公开(公告)号：US10943630B2

公开(公告)日：2021-03-09

申请号：US16731769

申请日：2019-12-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G11C7/10 ,  G06F13/16

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US10553264B2

公开(公告)日：2020-02-04

申请号：US15723532

申请日：2017-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Ran Kim ,  Seong-Hwan Jeon ,  Tae-Young Oh

IPC: G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00 ,  G11C7/22 ,  G06F13/16 ,  G11C7/10

Abstract: A memory device includes: a first clock receiver configured to receive a first clock signal; a second clock receiver configured to receive a second clock signal when data is input or output, wherein the second clock signal has a first clock frequency in a preamble period, and has a second clock frequency different from the first clock frequency after the preamble period; a command decoder configured to receive a clock synchronization command synchronized with the first clock signal and generate a clock synchronization signal, wherein the clock synchronization signal is generated during the preamble period; and a clock synchronizing circuit configured to generate a plurality of division clock signals in response to the second clock signal, latch the clock synchronization signal during the preamble period, and selectively provide the plurality of division clock signals as internal data clock signals according to a result of the latching.

公开(公告)号：US09959918B2

公开(公告)日：2018-05-01

申请号：US15298491

申请日：2016-10-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Ran Kim ,  Tae-Young Oh

IPC: G11C8/10 ,  G11C7/10 ,  G11C8/18 ,  G11C7/22 ,  G11C29/02

CPC classification number: G11C8/10 ,  G11C7/1072 ,  G11C7/222 ,  G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: An operating method of a memory device includes entering into a command bus training mode, generating a plurality of internal clock signals by dividing a received clock signal, generating a plurality of internal chip selection signals by latching a received chip selection signal according to the plurality of internal clock signals, generating a second command/address signal by encoding a received first command/address signal based on the plurality of internal chip selection signals, and outputting the second command/address signal.