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    MEMORY DEVICE AND METHOD FOR SYNCHRONIZING COMMAND START POINT (CSP)
    11.
    发明公开
    MEMORY DEVICE AND METHOD FOR SYNCHRONIZING COMMAND START POINT (CSP) 审中-公开

    公开(公告)号：US20240265957A1

    公开(公告)日：2024-08-08

    申请号：US18529876

    申请日：2023-12-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyeran KIM ,  Taeyoung OH

    IPC: G11C8/18

    CPC classification number: G11C8/18

    Abstract: Provided are a memory device and a method for command start point (CSP) synchronization. The memory device includes: a control logic circuit configured to receive command address (CA) signals and control an operation of the memory device; a clock circuit configured receive a clock signal and divide the clock signal to generate first to fourth phase clock signals that are respectively synchronized with first to fourth rising edges of the CA signals indicating a command start point (CSP) command, wherein the first to fourth rising edges of the CA signals constitute a command window; and a CA parity circuit configured to perform a command address parity (CAPAR) checking operation on the CSP command, wherein the CAPAR checking operation includes a plurality of operations respectively corresponding to rolling windows in which the command window is delayed by one clock cycle of the clock signal.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    17.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20220382464A1

    公开(公告)日：2022-12-01

    申请号：US17743137

    申请日：2022-05-12

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

    IPC: G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

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