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    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240201868A1

    公开(公告)日：2024-06-20

    申请号：US18588599

    申请日：2024-02-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

    IPC: G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

    Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

    MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME
    2.
    发明申请
    MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230067144A1

    公开(公告)日：2023-03-02

    申请号：US17692447

    申请日：2022-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408

    Abstract: A memory controller to control a semiconductor memory device, includes a row hammer management circuit and a scheduler. The row hammer management circuit counts each of access addresses associated with accesses to a plurality of memory cell rows of the semiconductor memory device to store counting values therein and determines a hammer address associated with at least one memory cell row which is intensively accessed among from the plurality of memory cell rows and a type of the hammer address associated with an urgency of management of the hammer address based on the counting values. The scheduler transmits the hammer address to the semiconductor memory device according to a different command protocol based on the type of the hammer address.

    OUTPUT DRIVER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    3.
    发明申请
    OUTPUT DRIVER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权

    公开(公告)号：US20220254383A1

    公开(公告)日：2022-08-11

    申请号：US17481995

    申请日：2021-09-22

    Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

    Inventor： Hyeran KIM ,  Junyeol LEE ,  Jung-Hoon CHUN

    IPC: G11C5/14 ,  G11C8/10

    Abstract: An output driver includes a pre driver including pre driving circuits, each including first and second pre pumps, and a main driver including main driving circuits, each including first and second main pumps. Each of the first and second pre pumps includes a first driving capacitor, and each of the first and second main pumps includes a second driving capacitor. During a first half cycle of a clock signal, the first pre pump and the first main pump perform a precharge operation, and the second pre pump and the second main pump perform a first driving operation, and during a second half cycle of the clock signal, the first pre pump and the first main pump perform the first driving operation, and the second pre pump and the second main pump perform the precharge operation. Capacitances of the first and second driving capacitors are different.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权

    公开(公告)号：US20230021622A1

    公开(公告)日：2023-01-26

    申请号：US17703049

    申请日：2022-03-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Kiheung KIM ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408 ,  H03M13/11 ,  H03M13/00

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240203475A1

    公开(公告)日：2024-06-20

    申请号：US18593937

    申请日：2024-03-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sungyong CHO ,  Kiheung KIM ,  Hyeran KIM

    IPC: G11C11/406 ,  G11C11/408 ,  H01L25/065 ,  H03M13/00 ,  H03M13/11

    CPC classification number: G11C11/40615 ,  G11C11/4085 ,  H03M13/1105 ,  H03M13/611 ,  H01L25/0657 ,  H01L2225/06541

    Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

    APPARATUS, MEMORY DEVICE AND METHOD FOR STORING PARAMETER CODES FOR ASYMMETRIC ON-DIE- TERMINATION
    9.
    发明申请
    APPARATUS, MEMORY DEVICE AND METHOD FOR STORING PARAMETER CODES FOR ASYMMETRIC ON-DIE- TERMINATION 有权

    公开(公告)号：US20220321125A1

    公开(公告)日：2022-10-06

    申请号：US17591093

    申请日：2022-02-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Daehyun KWON ,  Hyejung KWON ,  Hyeran KIM ,  Chisung OH

    IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17772 ,  H03K19/17736

    Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

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