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公开(公告)号：US20250117886A1
公开(公告)日：2025-04-10
申请号：US18882218
申请日：2024-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol Kim , Juntaek Kong , Seungwon Choi , Jongseong Choi
Abstract: The present disclosure relates to an image processing device to which contrast improvement effect may be applied, an image processing system, and a method of operating the same. An example method of operating an image processing device includes receiving an image including a plurality of pixels, splitting the image into a plurality of first regions, calculating a histogram for a second region that is greater than a first region of the plurality of first regions, generating a contrast conversion function based on the histogram for each of the plurality of first regions, and converting contrast of a current pixel among the plurality of pixels based on M×M first regions among the plurality of first regions adjacent to the current pixel. M is a natural number greater than or equal to 2.
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12.发明公开公开(公告)号：US20240243142A1
公开(公告)日：2024-07-18
申请号：US18408834
申请日：2024-01-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sanghyuck MOON , Jueun Park , Hyuncheol Kim , Eunsub Shim
IPC: H01L27/146
CPC classification number: H01L27/14612 , H01L27/14603 , H01L27/14636
Abstract: An image sensor, including a shared pixel including two sub pixels of a 1X2 structure and sharing a floating diffusion region on each of the two sub pixels through a metal wiring, unit pixels surrounding the floating diffusion region, within the shared pixel, separated from each other by front-side deep trench isolation, and each including a photodiode, a transfer transistor adjacent to the floating diffusion region and on each of the unit pixels, a reset transistor and a selection transistor on a first unit pixel located in a first quadrant among the unit pixels, a conversion gain transistor on a second unit pixel located in a second quadrant among the unit pixels, and a source follower transistor on a third unit pixel located in a third quadrant and a fourth unit pixel located in a fourth quadrant among the unit pixels.
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公开(公告)号：US12029029B2
公开(公告)日：2024-07-02
申请号：US17716215
申请日：2022-04-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghwan Lee , Yongseok Kim , Hyuncheol Kim , Dongsoo Woo , Sungwon Yoo
IPC: H10B12/00 , H01L29/423 , H01L29/792
CPC classification number: H10B12/50 , H01L29/4234 , H01L29/7926
Abstract: A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.
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公开(公告)号：US12016188B2
公开(公告)日：2024-06-18
申请号：US17840213
申请日：2022-06-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol Kim , Yongseok Kim , Dongsoo Woo , Kyunghwan Lee
CPC classification number: H10K19/202 , G11C13/0014 , G11C13/0069 , H10K10/50 , H10K85/221
Abstract: A semiconductor memory device includes a plurality of semiconductor patterns extending in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including a first source/drain area, a channel area, and a second source/drain area arranged in the first horizontal direction; a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas; a plurality of word lines on the upper surfaces or the side surfaces of the channel areas; and a plurality of resistive switch units respectively connected to first sidewalls of the semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including a first electrode, a second electrode, and a resistive switch material layer between the first and second electrodes and including carbon nanotubes.
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公开(公告)号：US20240128287A1
公开(公告)日：2024-04-18
申请号：US18374343
申请日：2023-09-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sanghyuck Moon , Jueun Park , Hyuncheol Kim , Jungbin Yun , Seungjoon Lee , Taesub Jung
IPC: H01L27/146
CPC classification number: H01L27/1461 , H01L27/14645 , H01L27/14689
Abstract: An image sensor including a substrate, at least one transfer gate on a top surface of the substrate, a floating diffusion region located in the substrate and disposed apart from the at least one transfer gate in a first direction, the first direction being parallel to the top surface of the substrate, an intrinsic semiconductor region located in the substrate and disposed between the at least one transfer gate and the floating diffusion region in the first direction, and a photoelectric conversion region located in the substrate and disposed apart from the floating diffusion region in a second direction, wherein the second direction is perpendicular to the first direction, and wherein the intrinsic semiconductor region is an undoped region.
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Patent Agency Ranking
公开(公告)号：US11670679B2
公开(公告)日：2023-06-06
申请号：US17225716
申请日：2021-04-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyunghwan Lee , Yongseok Kim , Hyuncheol Kim , Sungwon Yoo , Jaeho Hong
IPC: H01L29/00 , H01L29/10 , H01L29/786 , H01L29/06
CPC classification number: H01L29/1033 , H01L29/0615 , H01L29/7869 , H01L29/78642
Abstract: A semiconductor device includes a gate electrode on a substrate, a channel surrounding sidewalls of the gate electrode on the substrate, and source/drain electrodes on the substrate at opposite sides of the gate electrode in a first direction parallel to an upper surface of the substrate. A thickness of the channel from the gate electrode to the source/drain electrodes in a horizontal direction parallel to the upper surface of the substrate is not constant but varies in a vertical direction perpendicular to the upper surface of the substrate.
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公开(公告)号：US20230112070A1
公开(公告)日：2023-04-13
申请号：US17836228
申请日：2022-06-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minjun Lee , Yongseok Kim , Hyuncheol Kim , Jongman Park , Dongsoo Woo , Kyunghwan Lee
Abstract: Provided is a memory device. The memory device may include a substrate, a ferroelectric field effect transistor disposed on the substrate, a first channel contacting a gate structure of the ferroelectric field effect transistor and extending in a vertical direction from the gate structure of the ferroelectric field effect transistor, a selection word line disposed at one side of the first channel, a first gate dielectric layer disposed between the first channel and the selection word line, and a cell word line disposed on top of the first channel.
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公开(公告)号：US12268042B2
公开(公告)日：2025-04-01
申请号：US17746247
申请日：2022-05-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol Kim , Yongseok Kim , Dongsoo Woo , Kyunghwan Lee
Abstract: A variable resistance memory device including a stack including insulating sheets and conductive sheets, which are alternatingly stacked on a substrate, the stack including a vertical hole vertically penetrating therethrough, a bit line on the stack, a conductive pattern electrically connected to the bit line and vertically extending in the vertical hole, and a resistance varying layer between the conductive pattern and an inner side surface of the stack defining the vertical hole may be provided. The resistance varying layer may include a first carbon nanotube electrically connected to the conductive sheets, and a second carbon nanotube electrically connected to the conductive pattern.
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公开(公告)号：US12249651B2
公开(公告)日：2025-03-11
申请号：US17741219
申请日：2022-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyuncheol Kim , Yongseok Kim , Dongsoo Woo , Kyunghwan Lee
IPC: H01L29/78 , H01L29/10 , H01L29/417
Abstract: A semiconductor device includes: a channel; a gate structure on the channel; a first source/drain arranged at a first end of the channel and including a metal; a first tunable band-gap layer arranged between the channel and the first source/drain and having a band gap that changes according to stress; a first electrostrictive layer between the gate structure and the first tunable band-gap layer, the first electrostrictive layer having a property of being deformed based on and upon application of an electric field; and a second source/drain at a second end of the channel.
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公开(公告)号：US11996457B2
公开(公告)日：2024-05-28
申请号：US17443553
申请日：2021-07-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyuncheol Kim , Yongseok Kim , Ilgweon Kim , Seokhan Park , Kyunghwan Lee , Jaeho Hong
IPC: H01L29/423 , H01L23/482 , H01L29/66 , H01L29/78
CPC classification number: H01L29/4236 , H01L23/4828 , H01L29/66734 , H01L29/7813
Abstract: A semiconductor device includes a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first conductive pattern, a gate insulation pattern, a second conductive pattern and a second impurity region. Each of the semiconductor structures includes a first semiconductor pattern that has a linear shape that extends in a first direction and second semiconductor patterns that protrude from an upper surface of the first semiconductor pattern in a vertical direction. The semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction. The first conductive pattern is formed between the first semiconductor patterns. The first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion harrier pattern and a polysilicon pattern doped with impurities.
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