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    Semiconductor device
    12.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11842964B2

    公开(公告)日：2023-12-12

    申请号：US17323407

    申请日：2021-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78696

    Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

    INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS
    13.
    发明公开
    INTEGRATED CIRCUITS INCLUDING ABUTTED BLOCKS AND METHODS OF DESIGNING LAYOUTS OF THE INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20230297752A1

    公开(公告)日：2023-09-21

    申请号：US18162120

    申请日：2023-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Jisu Yu ,  Hyeongyu You ,  Minjae Jeong ,  Sanghoon Baek

    IPC: G06F30/392

    CPC classification number: G06F30/392

    Abstract: Integrated circuits including abutted blocks and methods of designing layouts of the integrated circuits are disclosed. The integrated circuit includes a first block having a first function cell array therein, which is at least partially surrounded by a first plurality of finishing cells, and a second block extending adjacent the first block. The second block includes a second function cell array therein, which is at least partially surrounded by a second plurality of finishing cells. The first plurality of finishing cells include: (i) a first finishing cell placed at a boundary of the integrated circuit, and (ii) a second finishing cell different from the first finishing cell, which is placed at a boundary between the first block and the second block.

    INTEGRATED CIRCUIT INCLUDING CELLS OF DIFFERENT HEIGHTS AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT
    15.
    发明申请
    INTEGRATED CIRCUIT INCLUDING CELLS OF DIFFERENT HEIGHTS AND METHOD OF DESIGNING THE INTEGRATED CIRCUIT 有权

    公开(公告)号：US20220382949A1

    公开(公告)日：2022-12-01

    申请号：US17877483

    申请日：2022-07-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Bonghyun LEE ,  Jungho Do

    IPC: G06F30/392 ,  H01L27/02 ,  H01L23/528

    Abstract: An integrated circuit includes a first column including a plurality of first cells aligned and placed in a plurality of first rows, each first row having a first width and extending in a first horizontal direction, a second column including a plurality of second cells aligned and placed in a plurality of second rows, each second row having a second width and extending in the first horizontal direction, and an interface column extending in a second horizontal direction perpendicular to the first horizontal direction between the first column and the second column, wherein the interface column includes at least one well tap configured to provide a first supply voltage to a well, and at least one substrate tap configured to provide a second supply voltage to a substrate.

    SEMICONDUCTOR DEVICES
    16.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20250087586A1

    公开(公告)日：2025-03-13

    申请号：US18960252

    申请日：2024-11-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

    Semiconductor device
    17.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12131999B2

    公开(公告)日：2024-10-29

    申请号：US18512527

    申请日：2023-11-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/786

    CPC classification number: H01L23/5286 ,  H01L27/0207 ,  H01L27/092 ,  H01L29/42392 ,  H01L29/78696

    Abstract: A semiconductor device includes a substrate having an active region, a first group of standard cells arranged in a first row on the active region of the substrate and having a first height defined in a column direction, a second group of standard cells arranged in a second row on the active region of the substrate, and having a second height, and a plurality of power lines extending in a row direction and respectively extending along boundaries of the first and the second groups of standard cells. The first and second groups of standard cells each further include a plurality of wiring lines extending in the row direction and arranged in the column direction, and at least some of wiring lines in at least one standard cell of the first and second groups of standard cells are arranged at different spacings and/or pitches.

    SEMICONDUCTOR DEVICES
    20.
    发明申请
    SEMICONDUCTOR DEVICES 有权

    公开(公告)号：US20220328408A1

    公开(公告)日：2022-10-13

    申请号：US17532052

    申请日：2021-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungho Do ,  Sanghoon Baek

    IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

    Abstract: Disclosed is a semiconductor device comprising a mixed height cell on a substrate, and a first power line and a second power line that run across the mixed height cell. First to third line tracks are defined between the first power line and the second power line. A fourth line track is defined adjacent to the second power line. The second power line is between the third line track and the fourth line track. The mixed height cell includes a plurality of lower lines aligned with the first to fourth line tracks. A cell height of the mixed height cell is about 1.25 times to about 1.5 times a distance between a first point of the first power line and a corresponding second point of the second power line.

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