公开(公告)号：US12034008B2

公开(公告)日：2024-07-09

申请号：US18336754

申请日：2023-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Baek ,  Jungho Do ,  Jaewoo Seo ,  Jisu Yu

IPC: H01L27/02 ,  H01L23/48 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L23/481 ,  H01L27/0207 ,  H01L2027/11829 ,  H01L2027/11864 ,  H01L2027/11881

Abstract: A semiconductor device includes a first standard cell disposed on a substrate in a first row and having a first cell height; a second standard cell disposed on the substrate in a second row, adjacent to the first row, second standard cell having a second cell height, different from the first cell height; and a power line extending in a first direction along a boundary between the first standard cell and the second standard cell.

公开(公告)号：US20230307436A1

公开(公告)日：2023-09-28

申请号：US18185414

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungho Do ,  Taejoong Song ,  Sanghoon Baek ,  Jisu Yu ,  Hyeongyu You ,  Minjae Jeong ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L27/0207 ,  H01L29/7851 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/0673 ,  H01L29/78696 ,  H01L27/0886

Abstract: An integrated circuit may include a first function cell and a second function cell each corresponding to a first circuit, wherein the first function cell may include a first pattern extending in a first direction along a first grid in a first layer and a second pattern extending in the first direction along a second grid in a second layer, the first grid may have a first pitch greater than a second pitch of the second grid in a second direction crossing the first direction, and the second function cell may include a layout of the first function cell and have a length greater than a length of the first function cell by the first pitch in the second direction.

公开(公告)号：US11755809B2

公开(公告)日：2023-09-12

申请号：US17458948

申请日：2021-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jaewoo Seo ,  Hyeongyu You ,  Sanghoon Baek ,  Jonghoon Jung

IPC: G06F30/00 ,  G06F30/392 ,  H01L23/50 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L23/50 ,  H01L27/0207

Abstract: An integrated circuit is provided. The integrated circuit includes a first cell that has a first height and is arranged in a first row which extends in a first direction; a second cell that has a second height and is arranged in a second row which extends in the first direction and is adjacent to the first row, wherein the second cell is adjacent to the first cell in a second direction perpendicular to the first direction; and a power line that extends in the first direction, is arranged on a boundary between the first cell and the second cell, and is configured to supply power to the first cell and the second cell. The first cell overlaps a first width of the power line along the second direction and the second cell overlaps a second width of the power line along the second direction, and the first width and the second width are different from each other.

公开(公告)号：US11557585B2

公开(公告)日：2023-01-17

申请号：US17154282

申请日：2021-01-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Ho Do ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/092 ,  G06F30/398 ,  G06F119/18

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

公开(公告)号：US11854610B2

公开(公告)日：2023-12-26

申请号：US18164199

申请日：2023-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  H10B10/00 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092

CPC classification number: G11C11/419 ,  G11C7/08 ,  H01L23/5286 ,  H01L27/092 ,  H10B10/12 ,  H10B10/18

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US11581038B2

公开(公告)日：2023-02-14

申请号：US17412588

申请日：2021-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yeop Baeck ,  Tae-Hyung Kim ,  Daeyoung Moon ,  Dong-Wook Seo ,  Inhak Lee ,  Hyunsu Choi ,  Taejoong Song ,  Jae-Seung Choi ,  Jung-Myung Kang ,  Hoon Kim ,  Jisu Yu ,  Sun-Yung Jang

IPC: G11C11/419 ,  G11C7/08 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor device includes an active area extending in a first direction, a first transistor including a first gate electrode and first source and drain areas disposed on the active area, the first source and drain areas being disposed at opposite sides of the first gate electrode, a second transistor including a second gate electrode and second source and drain areas disposed on the active area, the second source and drain areas being disposed at opposite sides of the second gate electrode, and a third transistor including a third gate electrode and third source and drain areas disposed on the active area, the third source and drain areas being disposed at opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction. The second transistor is configured to turn on and off, based on an operation mode of the semiconductor device.

公开(公告)号：US20210334449A1

公开(公告)日：2021-10-28

申请号：US17225773

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jisu Yu ,  Jaeho Park ,  Sanghoon Baek ,  Hyeongyu You ,  Seungyoung Lee ,  Seungman Lim

IPC: G06F30/398 ,  H01L23/528 ,  H01L29/423 ,  G06F30/392 ,  G06F30/3953

Abstract: A method includes placing standard cells based on a standard cell library and generating layout data, and placing a filler cell selected from among a first type filler cell and a second type filler cell by using the layout data. The filler cell is placed based on a density of a pattern formed in the standard cell. The standard cell library includes data defining the first and second type filler cells. A density of a contact formed on an active region of the second type filler cell to contact the active region of the second type filler cell is lower than a density of a contact formed on an active region of a first type filler cell to contact the active region of the first type filler cell.

公开(公告)号：US20190267366A1

公开(公告)日：2019-08-29

申请号：US16407919

申请日：2019-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  Woojin Rim ,  Jisu Yu ,  Jonghoon Jung

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  G03F1/36 ,  H01L23/522 ,  G06F17/50 ,  H01L27/118 ,  H01L21/8238 ,  H01L23/485

Abstract: A semiconductor device includes a substrate having a plurality of active patterns. A plurality of gate electrodes intersects the plurality of active patterns. An active contact is electrically connected to the active patterns. A plurality of vias includes a first regular via and a first dummy via. A plurality of interconnection lines is disposed on the vias. The plurality of interconnection lines includes a first interconnection line disposed on both the first regular via and the first dummy via. The first interconnection line is electrically connected to the active contact through the first regular via. Each of the vias includes a via body portion and a via barrier portion covering a bottom surface and sidewalls of the via body portion. Each of the interconnection lines includes an interconnection line body portion and an interconnection line barrier portion covering a bottom surface and sidewalls of the interconnection line body portion.

公开(公告)号：US20240234294A1

公开(公告)日：2024-07-11

申请号：US18393092

申请日：2023-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jisu Yu ,  Jungho Do ,  Sungyup Jung

IPC: H01L23/50 ,  H01L23/48 ,  H01L23/538 ,  H01L25/16

CPC classification number: H01L23/50 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/16

Abstract: An integrated circuit includes: a plurality of first power rails extending in a first horizontal direction and configured to provide a first power supply voltage that is applied thereto; a plurality of second power rails extending in the first horizontal direction and configured to provide a second power supply voltage that is applied thereto; and a power line in a switch cell area and extending in the first horizontal direction the power line being configured to provide a global power supply voltage that is applied thereto, wherein the plurality of first power rails and the plurality of second power rails are alternately arranged in a second horizontal direction vertical to the first horizontal direction, wherein the plurality of first power rails, the plurality of second power rails, and the power line form a front-side pattern on a same layer, and wherein the power line is provided between two second power rails adjacent to each other in the first horizontal direction, among the plurality of second power rails.

公开(公告)号：US20240105710A1

公开(公告)日：2024-03-28

申请号：US18469627

申请日：2023-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeongyu You ,  Jungho Do ,  Geonwoo Nam ,  Jisu Yu ,  Minjae Jeong ,  Jaehee Cho

IPC: H01L27/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0207 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/0928

Abstract: An integrated circuit includes a first cell in a first row extending in a first direction, a first power line extending in the first direction in a power rail layer, and configured to provide a first supply voltage to the first cell, and a first pattern overlapping a first boundary of the first row, and extending in the first direction in a first wiring layer, wherein the first cell includes at least one pattern extending in the first direction in the first wiring layer, and at least one transistor between the power rail layer and the first wiring layer, and the first pattern is configured to receive an input signal or an output signal of the first cell.