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    MAGNETIC MEMORY DEVICES
    11.
    发明公开
    MAGNETIC MEMORY DEVICES 审中-公开

    公开(公告)号：US20230180625A1

    公开(公告)日：2023-06-08

    申请号：US17817441

    申请日：2022-08-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Joonmyoung Lee ,  Junghwan Park ,  Jeong-Heon Park ,  Kyungil Hong

    IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

    CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L43/12

    Abstract: A magnetic memory device includes a first magnetic pattern and a second magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the first magnetic pattern and the second magnetic pattern, a lower electrode between the substrate and the first magnetic pattern, a blocking pattern between the lower electrode and the first magnetic pattern, a metal oxide pattern between the blocking pattern and the first magnetic pattern, and a buffer pattern between the metal oxide pattern and the first magnetic pattern. The lower electrode, the blocking pattern, the metal oxide pattern, and the buffer pattern include first, second, third, and fourth non-magnetic metals, respectively. The metal oxide pattern has an amorphous phase.

    Semiconductor devices with peripheral gate structures
    12.
    发明授权
    Semiconductor devices with peripheral gate structures 有权

    公开(公告)号：US11502082B2

    公开(公告)日：2022-11-15

    申请号：US16902338

    申请日：2020-06-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

    IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

    METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE
    13.
    发明申请
    METHOD OF MANUFACTURING A MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE 有权

    公开(公告)号：US20210043833A1

    公开(公告)日：2021-02-11

    申请号：US16840741

    申请日：2020-04-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jungmin Lee ,  Younghyun Kim ,  Junghwan Park ,  Sechung Oh ,  Kyungil Hong

    IPC: H01L43/12 ,  H01L43/08 ,  H01L21/02 ,  H01L27/22

    Abstract: In a method of manufacturing a magnetoresistive random access memory, a memory structure may be formed on a substrate. The memory structure may include a lower electrode, a magnetic tunnel junction (MTJ) structure, and an upper electrode sequentially stacked. A protection layer including silicon nitride may be formed to cover a surface of the memory structure. The protection layer may be formed by a chemical vapor deposition process using plasma and introducing deposition gases including a silicon source gas, a nitrogen source gas containing no hydrogen and a dissociation gas. Damages of the MTJ structure may be decreased during forming the protection layer. Thus, the MRAM may have improved characteristics.

    Semiconductor devices with peripheral gate structures
    14.
    发明授权
    Semiconductor devices with peripheral gate structures 有权

    公开(公告)号：US10714478B2

    公开(公告)日：2020-07-14

    申请号：US16532857

    申请日：2019-08-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-In Ryu ,  Taiheui Cho ,  Keunnam Kim ,  Kyehee Yeom ,  Junghwan Park ,  Hyeon-Woo Jang

    IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L21/768

    Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

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