公开(公告)号：US20130241037A1

公开(公告)日：2013-09-19

申请号：US13875731

申请日：2013-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junho Jeong ,  Sukhun Choi ,  Jangeun Lee ,  Kyunghyun Kim ,  Sechung Oh ,  Kyungtae Nam

IPC: H01L49/02

CPC classification number: H01L28/20 ,  H01L21/7684 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2436 ,  H01L43/12 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/147 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641

Abstract: Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided.

Abstract translation: 提供了制造半导体器件的方法，包括在衬底上形成电介质中间层，电介质层间限定开口。 在开口中形成金属图案。 对金属图案进行氧化处理以形成导电金属氧化物图案，并且导电金属氧化物图案被平坦化。 还提供了相关的半导体器件。

公开(公告)号：US12286707B2

公开(公告)日：2025-04-29

申请号：US17487088

申请日：2021-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonmyoung Lee ,  Whankyun Kim ,  Jeongheon Park ,  Junho Jeong

IPC: C23C14/56 ,  C23C14/08 ,  C23C16/40 ,  C23C16/54 ,  H01L21/67 ,  H10N50/01

Abstract: An apparatus for manufacturing a semiconductor device includes first and second process chambers in a first row in a first direction, third and fourth process chambers in a second row in the first direction, the third and fourth process chambers being spaced apart from the first and second process chambers in a second direction, and the first and third process chambers being arranged in parallel in the second direction to perform a same process, a load-lock chamber at one side of the first to fourth process chambers in the first direction, and first and second transfer chambers directly connected to each other in a third row in the first direction, the third row being between the first and second rows, and each of the first and second transfer chambers including a transfer unit to transfer a semiconductor substrate between the first to fourth process chambers and the load-lock chamber.

公开(公告)号：US20240423097A1

公开(公告)日：2024-12-19

申请号：US18525322

申请日：2023-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JeongMok KIM ,  Juhyun KIM ,  Se Chung OH ,  Junho Jeong

IPC: H10N50/20 ,  H10B61/00 ,  H10N50/01 ,  H10N50/85

Abstract: A memory device comprising a reference magnetic pattern and a free magnetic pattern sequentially stacked on a substrate; and a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, wherein the reference magnetic pattern includes: a first pinning pattern; a second pinning pattern between the first pinning pattern and the tunnel barrier pattern; and an exchange coupling pattern between the first pinning pattern and the second pinning pattern, the exchange coupling pattern antiferromagnetically coupling the first pinning pattern and the second pinning pattern, wherein the first pinning pattern includes: a first magnetic pattern; and a second magnetic pattern between the first magnetic pattern and the exchange coupling pattern, the first magnetic pattern is a single layer including an alloy of a first ferromagnetic element and a first non-magnetic metal element, and wherein the second magnetic pattern is a single layer including a second ferromagnetic element.

公开(公告)号：US11730064B2

公开(公告)日：2023-08-15

申请号：US16950009

申请日：2020-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Chul Lee ,  Whankyun Kim ,  Joonmyoung Lee ,  Junho Jeong

IPC: H10N52/80 ,  G11C11/18 ,  G11C11/16 ,  H10B61/00 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H10B61/22 ,  H10N52/00 ,  H10N52/01

Abstract: A magnetic memory device including a lower electrode on a substrate; a conductive line on the lower electrode; and a magnetic tunnel junction pattern on the conductive line, wherein the conductive line includes a first conductive line adjacent to the magnetic tunnel junction pattern; a second conductive line between the lower electrode and the first conductive line; and a high resistance layer at least partially between the first conductive line and the second conductive line, a resistivity of the second conductive line is lower than a resistivity of the first conductive line, and a resistivity of the high resistance layer is higher than the resistivity of the first conductive line and higher than the resistivity of the second conductive line.