公开(公告)号：US11086745B2

公开(公告)日：2021-08-10

申请号：US16573101

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Jae-Yong Jeong ,  Sung-Kyu Park ,  Beomkyu Shin ,  Young-Seok Hong

IPC: G11C8/00 ,  G06F11/30 ,  G06F11/10 ,  G06F13/16 ,  G11C11/16 ,  G06F12/02

Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

公开(公告)号：US20200241989A1

公开(公告)日：2020-07-30

申请号：US16573101

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Jae-Yong Jeong ,  Sung-Kyu Park ,  Beomkyu Shin ,  Young-Seok Hong

IPC: G06F11/30 ,  G06F11/10 ,  G06F13/16 ,  G06F12/02 ,  G11C11/16

Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.

公开(公告)号：US09824777B2

公开(公告)日：2017-11-21

申请号：US14796533

申请日：2015-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Jaegeun Park ,  Youngkwang Yoo ,  Biwoong Chung

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/54

CPC classification number: G11C29/42 ,  G11C29/44 ,  G11C29/789 ,  G11C2029/4402

Abstract: A storage system is provided which includes: a storage device including a first memory, which may be nonvolatile memory, and a second memory, which may be a device memory, and configured to request a test on at least one of the first and second memories; and a host configured to test the at least one memory in response to the request for the memory test from the storage device and store the test result in the first memory or a third memory.

公开(公告)号：US09128623B2

公开(公告)日：2015-09-08

申请号：US14660897

申请日：2015-03-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kui-Yon Mun ,  Heewon Lee

IPC: G06F12/00 ,  G06F3/06 ,  G11C16/10 ,  G11C29/52 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0688 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/52

Abstract: Random sequence data is sequentially generated based on a seed assigned to a selected memory space, and one of access-requested segments of the selected memory space is logically combined with the sequentially generated random sequence data to transfer the access-requested segment. The sequentially generating and the logically combining are iteratively performed until remaining access-requested segments all transferred.