公开(公告)号：US20220157823A1

公开(公告)日：2022-05-19

申请号：US17592555

申请日：2022-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyooho JUNG ,  Jeong-gyu SONG ,  Younsoo KIM ,  Jooho LEE

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a capacitor including first and second electrodes and a dielectric layer. The dielectric layer may include a zirconium aluminum oxide layer including a first zirconium region adjacent to the first electrode, a first aluminum region, a second aluminum region adjacent to the second electrode, and a second zirconium region between the first and second aluminum regions. The first and second zirconium regions may include zirconium and oxygen and may be devoid of aluminum. The first and second aluminum regions may include aluminum and oxygen and may be devoid of zirconium. The first aluminum region and the first zirconium region may be spaced apart by a first distance, and the first aluminum region and the second zirconium region may be spaced apart by a second distance shorter than the first distance.

公开(公告)号：US20210384194A1

公开(公告)日：2021-12-09

申请号：US17172131

申请日：2021-02-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Su WOO ,  Haeryong KIM ,  Younsoo KIM ,  Sunmin MOON ,  Jeonggyu SONG ,  Kyooho JUNG

IPC: H01L27/108

Abstract: A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.

公开(公告)号：US20210134804A1

公开(公告)日：2021-05-06

申请号：US16897589

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyooho JUNG ,  Younsoo KIM ,  Young-lim PARK ,  Jeong-Gyu SONG ,  Se Hyoung AHN ,  Changmu AN

IPC: H01L27/108 ,  H01L49/02 ,  H01L21/02

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a capacitor that includes a bottom electrode, a top electrode opposite to the bottom electrode across a dielectric layer, and an interface layer between the bottom electrode and the dielectric layer. The interface layer includes a combination of niobium (Nb), titanium (Ti), oxygen (O), and nitrogen (N), and further includes a constituent of the dielectric layer.

公开(公告)号：US20200273698A1

公开(公告)日：2020-08-27

申请号：US16520990

申请日：2019-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggyu SONG ,  Kyooho JUNG ,  Yongsung KIM ,  Jeongil BANG ,  Jooho LEE ,  Junghwa KIM ,  Haeryong KIM ,  Myoungho JEONG

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L21/768

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are included. The method of manufacturing the semiconductor device includes forming a hafnium oxide layer on a substrate and crystallizing the hafnium oxide layer by using a hafnium cobalt oxide layer as a seed layer. According to the method of manufacturing the semiconductor device, a thin-film hafnium oxide layer may be easily crystallized.

公开(公告)号：US20240064999A1

公开(公告)日：2024-02-22

申请号：US18185586

申请日：2023-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyooho JUNG

IPC: H10B63/10 ,  H10B63/00

CPC classification number: H10B63/10 ,  H10B63/84

Abstract: A data storage structure may include a lower electrode, a dielectric layer on the lower electrode, and an upper electrode on the dielectric layer. The dielectric layer may include a metal compound having a crystalline phase and including a first metal. The dielectric layer also may include a phase control material located in an interfacial region of the dielectric layer, adjacent to the upper electrode. The phase control material may include at least one of a second metal and a metal nitride. The second metal may be configured to induce a phase change in the metal compound of the dielectric layer. The metal nitride may include the second metal.

公开(公告)号：US20230420490A1

公开(公告)日：2023-12-28

申请号：US18465439

申请日：2023-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggyu SONG ,  Kyooho JUNG ,  Younsoo KIM ,  Haeryong KIM ,  Jooho LEE

IPC: H10B12/00 ,  H01L21/285

CPC classification number: H01L28/60 ,  H01L21/28556 ,  H10B12/30

Abstract: A capacitor includes: a lower electrode including a metal nitride represented by MM′N, wherein M is a metal element, M′ is an element different from M, and N is nitrogen; a dielectric layer on the lower electrode; an interfacial layer between the lower electrode and the dielectric layer and including a metal nitrate represented by MM′ON, wherein M is a metal element, M′ is an element different from M, N is nitrogen, and O is oxygen; and an upper electrode on the dielectric layer.

公开(公告)号：US20230345705A1

公开(公告)日：2023-10-26

申请号：US18215301

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyooho JUNG ,  Yukyung SHIN ,  Jinho LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

Abstract: A semiconductor device including a substrate; bottom electrodes on the substrate, each bottom electrode including a first region and a second region, the second region containing an additional element relative to the first region; a first supporting pattern on the substrate and in contact with a portion of a side surface of each bottom electrode; a top electrode on the bottom electrodes; a dielectric layer between the bottom electrodes and the top electrode; and a capping layer between the bottom electrodes and the dielectric layer, the capping layer covering a top surface and a bottom surface of the first supporting pattern, wherein the second region is in contact with the capping layer, and the capping layer and the dielectric layer include different materials from each other.

公开(公告)号：US20230255019A1

公开(公告)日：2023-08-10

申请号：US18136984

申请日：2023-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Su WOO ,  Haeryong KIM ,  Younsoo KIM ,  Sunmin MOON ,  Jeonggyu SONG ,  Kyooho JUNG

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/34

Abstract: A semiconductor device includes conductive pillars on a semiconductor substrate, a first support pattern that contacts first portions of lateral surfaces of the conductive pillars and connects the conductive pillars to each other, the first support pattern including first support holes that expose second portions of the lateral surfaces of the conductive pillars, a capping conductive pattern that contacts the second portions of the lateral surfaces of the conductive pillars and exposes the first support pattern, the second portions of the lateral surfaces of the conductive pillars being in no contact with the first support pattern, and a dielectric layer that covers the first support pattern and the capping conductive pattern, the dielectric layer being spaced apart from the conductive pillars.

公开(公告)号：US20220278192A1

公开(公告)日：2022-09-01

申请号：US17749240

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonggyu SONG ,  Kyooho JUNG ,  Younsoo KIM ,  Haeryong KIM ,  Jooho LEE

IPC: H01L49/02 ,  H01L21/285 ,  H01L27/108

Abstract: A capacitor includes: a lower electrode including a metal nitride represented by MM′N, wherein M is a metal element, M′ is an element different from M, and N is nitrogen; a dielectric layer on the lower electrode; an interfacial layer between the lower electrode and the dielectric layer and including a metal nitrate represented by MM′ON, wherein M is a metal element, M′ is an element different from M, N is nitrogen, and O is oxygen; and an upper electrode on the dielectric layer.

公开(公告)号：US20220085010A1

公开(公告)日：2022-03-17

申请号：US17361418

申请日：2021-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyooho JUNG ,  Young-Lim PARK ,  Changmu AN ,  Hongseon SONG ,  Yukyung SHIN

IPC: H01L27/08 ,  H01L49/02

Abstract: Disclosed are semiconductor devices and fabrication methods for the same. The semiconductor devices may include a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked on a semiconductor substrate. The bottom electrode includes a first doping region in contact with the dielectric layer, a main region spaced apart from the dielectric layer by the first doping region intervening therebetween, and a second doping region between the first doping region and the main region. Each of the first and second doping regions includes oxygen and a doping metal. In some embodiments, the second doping region may include nitrogen. The main region may be devoid of the doping metal. An amount of oxygen in the second doping region is less than an amount of oxygen in the first doping region.