公开(公告)号：US20220157810A1

公开(公告)日：2022-05-19

申请号：US17359110

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Lim SUK ,  Seokhyun LEE ,  Jaegwon JANG

IPC: H01L27/08 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522 ,  H01L49/02

Abstract: Disclosed is a semiconductor package including: a redistribution substrate; at least one passive device in the redistribution substrate, the passive device including a first terminal and a second terminal; and a semiconductor chip on a top surface of the redistribution substrate, the semiconductor chip vertically overlapping at least a portion of the passive device, wherein the redistribution substrate includes: a dielectric layer in contact with a first lateral surface, a second lateral surface opposite to the first lateral surface, and a bottom surface of the passive device; a lower conductive pattern on the first terminal; a lower seed pattern provided between the first terminal and the conductive pattern, and directly connected to the first terminal; a first upper conductive pattern on the second terminal and a first upper seed pattern provided between the second terminal and the first upper conductive pattern, and directly connected to the second terminal

公开(公告)号：US20220068818A1

公开(公告)日：2022-03-03

申请号：US17213506

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung SONG ,  Kyoung Lim SUK ,  Jaegwon JANG ,  Wonkyoung CHOI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

公开(公告)号：US20250062208A1

公开(公告)日：2025-02-20

申请号：US18623645

申请日：2024-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim SUK ,  Kyung Don MUN ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor package may include a first redistribution layer structure, a chiplet structure on the first redistribution layer structure, a plurality of first connection members on the first redistribution layer structure, a first molding material on the first redistribution layer structure and molding the chiplet structure and the plurality of first connection members, and a second redistribution layer structure on the first molding material. The chiplet structure may include a third redistribution layer structure, a first chiplet and a second chiplet on the third redistribution layer structure, and a bridge die on a bottom surface of the third redistribution layer structure.

公开(公告)号：US20240178122A1

公开(公告)日：2024-05-30

申请号：US18226352

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Sangjin BAEK ,  Kyoung Lim SUK ,  Shang-Hoon SEO ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311

Abstract: A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.

公开(公告)号：US20190051607A1

公开(公告)日：2019-02-14

申请号：US16010872

申请日：2018-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim SUK ,  SEOKHYUN LEE

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/14 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: Insulating layers of a redistribution layer of a semiconductor package may be formed as a polymer film having inorganic fillers formed therein. The inorganic fillers may trap reactive materials to inhibit and/or substantially prevent the metal conductors, such as chip pads of the semiconductor chip being packaged, from being damaged by the reactive material. As a result, the reliability and the durability of the semiconductor package may be improved.