公开(公告)号：US20240170408A1

公开(公告)日：2024-05-23

申请号：US18426995

申请日：2024-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Inhyung SONG ,  Kyoung Lim SUK ,  Jaegwon JANG ,  Wonkyoung CHOI

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5384 ,  H01L23/3114 ,  H01L23/5386 ,  H01L24/14

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

公开(公告)号：US20240047324A1

公开(公告)日：2024-02-08

申请号：US18183699

申请日：2023-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Dongwook KIM ,  Kyounglim SUK ,  Inhyung SONG ,  Sehoon JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L24/32 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/105 ,  H01L24/73 ,  H01L24/05 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/16227 ,  H01L2224/0401 ,  H01L2225/1058 ,  H01L2224/05008

Abstract: A semiconductor package includes a redistribution wiring layer having a first surface and a second surface opposite to the first surface, a conductive bump on the first surface, and a first semiconductor device on the conductive bump. The redistribution wiring layer includes redistribution wirings having an uppermost redistribution wiring, a bonding pad, and an uppermost insulating layer. The uppermost redistribution wiring has a redistribution via and a redistribution line on the redistribution via. The bonding pad disposes on the redistribution line of the uppermost redistribution wiring, and the conductive bump is disposed on the bonding pad. The uppermost insulating layer overlapping (e.g., covering) the uppermost redistribution wiring and having an opening exposing a portion of the bonding pad.

公开(公告)号：US20240145375A1

公开(公告)日：2024-05-02

申请号：US18311405

申请日：2023-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjeong HWANG ,  Dongkyu KIM ,  Inhyung SONG

IPC: H01L23/498 ,  H01L21/02 ,  H01L21/768 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/02164 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76873 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29187 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81895 ,  H01L2224/83896 ,  H01L2225/1041 ,  H01L2924/182

Abstract: A semiconductor package includes an interposer including a first redistribution layer and a second redistribution layer that is on the first redistribution layer and is electrically coupled to the first redistribution layer; and a semiconductor chip on the interposer. The first redistribution layer includes a first organic insulating layer and a plurality of first conductors in the first organic insulating layer. The second redistribution layer includes a second organic insulating layer, a first silicon insulating layer on the second organic insulating layer, and a plurality of second conductors penetrating through both the second organic insulating layer and the first silicon insulating layer. The semiconductor chip includes a second silicon insulating layer and a plurality of third conductors in the second silicon insulating layer. The second conductors are directly bonded to separate, respective third conductors and the first silicon insulating layer is directly bonded to the second silicon insulating layer.

公开(公告)号：US20240096815A1

公开(公告)日：2024-03-21

申请号：US18244739

申请日：2023-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegwon JANG ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/544 ,  H01L23/498 ,  H01L25/10 ,  H01L25/16

CPC classification number: H01L23/544 ,  H01L23/49822 ,  H01L25/105 ,  H01L25/16 ,  H01L24/48 ,  H01L2223/54426 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes: a first package substrate including a first redistribution structure; a second package substrate including a second redistribution structure; a semiconductor chip provided between the first package substrate and the second package substrate, and attached to the first package substrate; and a fiducial mark provided on the second package substrate and separated from the second redistribution structure in a plan view.

公开(公告)号：US20240088055A1

公开(公告)日：2024-03-14

申请号：US18368309

申请日：2023-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung SONG ,  Jaegwon Jang ,  Yeonho Jang

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/20 ,  H01L25/105 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2224/16227 ,  H01L2224/21

Abstract: A semiconductor package includes a base structure having a fan-in area and fan-out areas surrounding the fan-in area, a semiconductor chip in the fan-in area, a package body layer in the fan-in area and the fan-out areas and covering the semiconductor chip, a redistribution structure on the package body layer, and alignment marks on the redistribution structure in a plan view. Each of the alignment marks includes a plurality of metal layers, and a plurality of auxiliary patterns are in the redistribution structure under the alignment marks to assist in recognition of the alignment marks.

公开(公告)号：US20240203961A1

公开(公告)日：2024-06-20

申请号：US18226180

申请日：2023-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyeonjeong HWANG ,  Kyoung Lim SUK ,  Inhyung SONG

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/32 ,  H01L25/162 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/16227 ,  H01L2224/32265 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19106

Abstract: A semiconductor package may include a first redistribution substrate, a semiconductor chip disposed on the first redistribution substrate, a mold layer covering the semiconductor chip and including a first opening exposing a portion of a top surface of the semiconductor chip, a first passive device disposed on the portion of the top surface of the semiconductor chip exposed by the first opening, an insulating pattern filling the first opening and covering at least a portion of the first passive device, and a second redistribution substrate disposed on the mold layer. The first passive device may be spaced apart from the mold layer, with the insulating pattern interposed therebetween.

公开(公告)号：US20230071812A1

公开(公告)日：2023-03-09

申请号：US17846245

申请日：2022-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaegwon JANG ,  Kyounglim SUK ,  Inhyung SONG

IPC: H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a substrate including a redistribution layer, a chip structure including a first semiconductor chip disposed on the substrate and including a first through-electrode, a second semiconductor chip disposed on the first semiconductor chip and electrically connected to the first semiconductor chip by the first through-electrode, and a first encapsulant at least partially surrounding the second semiconductor chip. A first connection bump disposed between the substrate and the chip structure and electrically connects the first through-electrode to the redistribution layer, a second connection bump disposed below the substrate and electrically connects to the redistribution layer, and a second encapsulant e the chip structure on the substrate. The first semiconductor chip is connected to and faces the second semiconductor chip.

公开(公告)号：US20220068818A1

公开(公告)日：2022-03-03

申请号：US17213506

申请日：2021-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Inhyung SONG ,  Kyoung Lim SUK ,  Jaegwon JANG ,  Wonkyoung CHOI

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor device on a first redistribution substrate, a first mold layer that covers the first semiconductor device and the first redistribution substrate, and a second redistribution substrate on the first mold layer, the second redistribution substrate including a first opening that exposes a top surface of the first mold layer, a sidewall of the second redistribution substrate that is exposed to the first opening having a stepwise structure.

公开(公告)号：US20250062208A1

公开(公告)日：2025-02-20

申请号：US18623645

申请日：2024-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoung Lim SUK ,  Kyung Don MUN ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

Abstract: A semiconductor package may include a first redistribution layer structure, a chiplet structure on the first redistribution layer structure, a plurality of first connection members on the first redistribution layer structure, a first molding material on the first redistribution layer structure and molding the chiplet structure and the plurality of first connection members, and a second redistribution layer structure on the first molding material. The chiplet structure may include a third redistribution layer structure, a first chiplet and a second chiplet on the third redistribution layer structure, and a bridge die on a bottom surface of the third redistribution layer structure.

公开(公告)号：US20240178122A1

公开(公告)日：2024-05-30

申请号：US18226352

申请日：2023-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyung Don MUN ,  Sangjin BAEK ,  Kyoung Lim SUK ,  Shang-Hoon SEO ,  Inhyung SONG ,  Yeonho JANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15311

Abstract: A semiconductor package, including a first redistribution substrate, a semiconductor chip on the first redistribution substrate, a connection structure on the first redistribution substrate and spaced apart from the semiconductor chip, the connection structure including a connection substrate and a post on the connection substrate, a second redistribution substrate on the semiconductor chip and the connection structure, and a molding layer between the first redistribution substrate and the second redistribution substrate, the molding layer encapsulating the semiconductor chip and the connection structure, wherein the connection substrate includes a conductive pattern that vertically penetrates the connection substrate, the post is in contact with a top surface of the conductive pattern, and a width of the post is less than a width of the connection substrate.