公开(公告)号：US20190254040A1

公开(公告)日：2019-08-15

申请号：US16395980

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Min LEE ,  Tak Ki YU ,  Yung Soo KIM

IPC: H04W72/08 ,  H04W72/04 ,  H04W24/08 ,  H04W16/32

CPC classification number: H04W72/082 ,  H04W16/32 ,  H04W24/08 ,  H04W72/042 ,  H04W72/0433 ,  H04W72/0446 ,  H04W88/08

Abstract: A method for mitigating interference at a small base station in a hierarchical cell structure is provided. In the method, the small base station checks a sub-frame allocated to macro user equipment by using a downlink signal received from a macro base station when an interference candidate user equipment list is received. The interference candidate user equipment list contains information on the macro user equipment adjacent to a femto cell controlled by the small base station. Then the small base station allocates other sub-frame to femto user equipment located in the femto cell by avoiding the sub-frame allocated to the macro user equipment.

公开(公告)号：US20190189613A1

公开(公告)日：2019-06-20

申请号：US16174702

申请日：2018-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taewon HA ,  Juyoun KIM ,  Sang Min LEE ,  Moon-Sun HONG ,  Seki HONG

IPC: H01L27/088 ,  H01L21/28 ,  H01L29/51 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28158 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L29/41791 ,  H01L29/517 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a substrate having an active region, and first to third transistors on the active region of the substrate, each of the first to third transistors including a dielectric layer on the substrate, a metal layer on the dielectric layer, a barrier layer between the dielectric layer and the metal layer, and a work function layer between the dielectric layer and the barrier layer, wherein the barrier layer of the third transistor is in contact with the dielectric layer of the third transistor, and wherein a threshold voltage of the second transistor is greater than a threshold voltage of the first transistor and less than a threshold voltage of the third transistor.

公开(公告)号：US20180075928A1

公开(公告)日：2018-03-15

申请号：US15648909

申请日：2017-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Min LEE ,  Jae Hyung CHOI

IPC: G11C29/52 ,  G06F1/12

CPC classification number: G11C29/52 ,  G01R31/2834 ,  G06F1/12 ,  G11C29/023 ,  G11C29/028 ,  G11C29/56012

Abstract: A memory system includes a memory device, and a memory controller. The controller adjusts a delay of a data strobe clock, performs at least one of a read test and a write test on the memory device, detect at least one data bit, which reduces at least one margin of a setup margin and a hold margin, from among a plurality of data bits, and adjusts a delay of the at least one data bit to allow the at least one margin to increase.