公开(公告)号：US20230025237A1

公开(公告)日：2023-01-26

申请号：US17693571

申请日：2022-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghae LEE ,  Buil NAM ,  Jinsun YEOM ,  Sangwan NAM ,  Jaein LEE

IPC: G11C29/38 ,  G11C16/30 ,  G11C16/08 ,  G11C16/04 ,  G11C29/12

Abstract: A nonvolatile memory device includes a memory cell array, a voltage generator, a voltage path circuit and a wordline defect detection circuit. The memory cell array includes memory cells and wordlines connected to the memory cells. The voltage generator generates a wordline voltage applied to the wordlines. The voltage path circuit between the voltage generator and the memory cell array transfers the wordline voltage to the wordlines. The wordline defect detection circuit is connected to a measurement node between the voltage generator and the voltage path circuit. The wordline defect detection circuit measures a path leakage current of the voltage path circuit based on a measurement voltage of the measurement node to generate an offset value corresponding to the path leakage current in a compensation mode and determines defect of each wordline of the wordlines based on the offset value and the measurement voltage in a defect detection mode.

公开(公告)号：US20230018305A1

公开(公告)日：2023-01-19

申请号：US17947320

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaehoon KIM ,  Junyoung KO ,  Sangwan NAM ,  Minjae SEO ,  Jiwon SEO ,  Hojun LEE

IPC: G11C16/08 ,  G11C16/20 ,  G11C16/16 ,  G11C16/04 ,  G11C16/30 ,  G11C16/34 ,  G11C16/26

Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

公开(公告)号：US20220139457A1

公开(公告)日：2022-05-05

申请号：US17234175

申请日：2021-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaehoon KIM ,  Junyoung KO ,  Sangwan NAM ,  Minjae SEO ,  Jiwon SEO ,  Hojun LEE

IPC: G11C16/08 ,  G11C16/20 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C16/04

Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.

公开(公告)号：US20220075565A1

公开(公告)日：2022-03-10

申请号：US17455037

申请日：2021-11-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Jaeduk YU ,  Sangwan NAM ,  Sangwon PARK ,  Daeseok BYEON ,  Bongsoon LIM

IPC: G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US20220005539A1

公开(公告)日：2022-01-06

申请号：US17156801

申请日：2021-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung KIM ,  Sehwan PARK ,  Ilhan PARK ,  Sangwan NAM

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/18

Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.

公开(公告)号：US20210201982A1

公开(公告)日：2021-07-01

申请号：US16935712

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk CHOI ,  Sangwan NAM

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/409 ,  G11C5/06 ,  G11C5/02

Abstract: A memory device includes a memory cell array including cell strings, respectively connected between string select lines and ground select lines, and wordlines connected to memory cells, a control logic to generate a first voltage provided to the string select lines, and a second voltage provided to the ground select lines, and to adjust voltage levels of the first and second voltages to control a channel boosting level of the cell strings, and a row decoder to provide a read voltage, a read pass voltage, and the first and second voltages to the memory cell array under control of the control logic. The control logic generates one of the first and second voltage as a pre-pulse voltage. The row decoder provides a third voltage to at least one of the wordlines.