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公开(公告)号:US20170352640A1
公开(公告)日:2017-12-07
申请号:US15684425
申请日:2017-08-23
发明人: JaeYong PARK , Junyoung KO , Whasu SIN , Kyhyun JUNG
CPC分类号: H01L24/799 , B23K1/0016 , B23K1/0056 , B23K1/018 , B23K26/38 , B23K2101/42 , H01L24/98 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/00 , H01L2924/014 , H01L2924/12042 , H05K13/0486 , Y10T29/49821 , Y10T29/53274
摘要: A removal apparatus for a semiconductor chip may include a stage configured to support a board on which the semiconductor chip is mounted by bumps, a laser configured to irradiate a laser beam into the board over an area larger than the semiconductor chip, and a picker configured to cause the laser beam to penetrate the semiconductor chip locally and to separate the semiconductor chip from the board. A method of removing a semiconductor chip from a board may include loading the board, on which the semiconductor chip is mounted by bumps, on a stage; irradiating a laser beam into the semiconductor chip to melt the bumps and to separate the semiconductor chip from the board; continuously irradiating the laser beam into the board on which solder pillars, that are residues of the bumps, remain to melt the solder pillars; and removing the solder pillars.
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公开(公告)号:US20150179601A1
公开(公告)日:2015-06-25
申请号:US14632657
申请日:2015-02-26
发明人: JaeYong PARK , Junyoung KO , Whasu SIN , Kyhyun JUNG
CPC分类号: H01L24/799 , B23K1/0016 , B23K1/0056 , B23K1/018 , B23K26/38 , B23K2101/42 , H01L24/98 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2924/00 , H01L2924/014 , H01L2924/12042 , H05K13/0486 , Y10T29/49821 , Y10T29/53274
摘要: An apparatus for removing a semiconductor chip from a board may include: a laser configured to irradiate the board with a laser beam to heat bumps mounting the semiconductor chip on the board; a picker configured to separate the semiconductor chip from the board; a vacuum portion configured to provide a vacuum to the picker; and an intake. If solder pillars, that are residues of the bumps, are melted by the laser beam, the intake removes the solder pillars using the vacuum provided from the vacuum portion. An apparatus for removing a semiconductor chip from a board may include: a stage configured to support the board on which the semiconductor chip is mounted by bumps; a laser configured to irradiate the board with a laser beam to heat the bumps mounting the semiconductor chip on the board; and a picker configured to separate the semiconductor chip from the board.
摘要翻译: 一种用于从板上去除半导体芯片的装置可以包括:激光器,被配置成用激光束照射板,以加热将半导体芯片安装在板上的凸块; 拾取器,被配置为将半导体芯片与板分离; 真空部分,被配置为向拾取器提供真空; 和摄入。 如果作为凸块的残留物的焊料柱被激光束熔化,则吸入件使用从真空部分提供的真空去除焊料柱。 用于从板上去除半导体芯片的装置可以包括:被配置为通过凸块来支撑半导体芯片安装在其上的板的台; 激光器,被配置为用激光束照射所述板,以加热将所述半导体芯片安装在所述板上的所述凸块; 以及构造成将半导体芯片与板分离的拾取器。
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公开(公告)号:US20230395180A1
公开(公告)日:2023-12-07
申请号:US18133319
申请日:2023-04-11
发明人: Junyoung KO , Jungmin Bak , Changhwi Park
IPC分类号: G11C29/50 , G11C11/408
CPC分类号: G11C29/50004 , G11C11/4087 , G11C11/4085
摘要: A row decoder circuit includes a first transistor connected to a power supply node and a first node; a plurality of second nodes connected in parallel between the first node and a power ground node, each of the plurality of second nodes being connected to a corresponding word line among the plurality of word lines; a plurality of second transistors connected between the first node and the plurality of second nodes; a plurality of third transistors connected between the plurality of second nodes and a power ground node; a comparator outputting a detection signal by receiving a voltage of the first node and a reference voltage. In a pre-charging period, the first transistor is turned on, the plurality of second transistors are turned on, and the third transistors are turned off, so that the first node and the plurality of second nodes are charged. In a development period, the first transistor maintains a turned-on state, the plurality of second transistors are turned off, and each of the second nodes is discharged at a different rate depending on whether current of the corresponding word line is leaked, and in a sensing period, the first transistor is turned off, the plurality of second transistors are turned on, and the first node is selectively discharged according to voltage levels of the discharged second nodes.
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公开(公告)号:US20210141014A1
公开(公告)日:2021-05-13
申请号:US16916679
申请日:2020-06-30
发明人: Chansik KWON , Junyoung KO , Jongkeun MOON , Jinduck PARK , Jiyeon HAN
摘要: A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.
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公开(公告)号:US20230387054A1
公开(公告)日:2023-11-30
申请号:US18120866
申请日:2023-03-13
发明人: Junyoung KO
IPC分类号: H01L23/00
CPC分类号: H01L24/06 , H01L24/14 , H01L2224/04042 , H01L2224/02372 , H01L2224/0603 , H01L2224/06169 , H01L2224/1403 , H01L2224/14051 , H01L2224/1416
摘要: A semiconductor package is provided. The semiconductor package includes a substrate including first and second surfaces opposite to each other, a redistribution layer on the first surface and having third and fourth surfaces opposite to each other wherein the third surface of the redistribution layer faces the first surface, a semiconductor chip between the substrate and the redistribution layer, the semiconductor chip spaced apart from the first surface and electrically connected to the third surface, a connection structure between the substrate and the redistribution layer and horizontally spaced apart from the semiconductor chip wherein the connection structure is electrically connected to the first surface and the third surface, and a dielectric layer between the substrate and the redistribution layer. The dielectric layer covers the semiconductor chip and the connection structure and extends between the semiconductor chip and the first surface.
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公开(公告)号:US20230018305A1
公开(公告)日:2023-01-19
申请号:US17947320
申请日:2022-09-19
发明人: Chaehoon KIM , Junyoung KO , Sangwan NAM , Minjae SEO , Jiwon SEO , Hojun LEE
摘要: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.
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公开(公告)号:US20220139457A1
公开(公告)日:2022-05-05
申请号:US17234175
申请日:2021-04-19
发明人: Chaehoon KIM , Junyoung KO , Sangwan NAM , Minjae SEO , Jiwon SEO , Hojun LEE
摘要: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.
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